1,726,451 research outputs found
Dataflow modeling for reconfigurable signal processing systems
No full textNowadays, adaptive signal processing systems have become a reality. Their development has been mainly driven by the need of satisfying diverging constraints and changeable user needs, like resolution and throughput versus energy consumption. System runtime tuning, based on constraints/conditions variations, can be effectively achieved by adopting reconfigurable computing infrastructures. These latter could be implemented either at the hardware or at the software level, but in any case their management and subsequent implementation is not trivial. In this chapter we present how dataflow models properties, as predictability and analyzability, can ease the development of reconfigurable signal processing systems, leading designers from modelling to physical system deployment
Arithmetic
No full textHandbook of Signal Processing Systems is organized in three parts. The first part motivates representative applications that drive and apply state-of-the art methods for design and implementation of signal processing systems; the second part discusses architectures for implementing these applications; the third part focuses on compilers and simulation tools, describes models of computation and their associated design tools and methodologies. This handbook is an essential tool for professionals in many fields and researchers of all levels.</p
Real-time compensation of static distortion by measurement of differential noise gain
No full textIt is well-known that in a cascaded system of amplifiers the majority of noise is due to the first stage and the majority of distortion due to the final stage. Consequently, the observed noise at the output is subject to the same nonlinear process as the signal of interest. We use this fact to characterise the distorting process and linearise the system in real-time using statistical measurements of this noise
Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design
No full textComplexity management, portability and long term adaptivity are common challenges in different fields of embedded systems, normally colliding with the needs of efficient resource utilization and power balance. Image/signal processing systems, though required to offer a large variety of complex functions, have also to deal with battery-life limitations. Wearable signal processing systems, for example, should provide high performance and support new generation standards without compromising their portability and their long-term usability. These constraints challenge hardware designers: early stage trade-off analysis and power management automated techniques are helpful to guarantee a reasonable time-to-market. In the field of video codec specifications, the MPEG standard known as Reconfigurable Video Coding (RVC) framework addresses functional complexity and adaptivity leveraging on the intrinsic modularity of the dataflow model of computation, but it still lacks in offering power management support. The main contribution of this work is providing an automatic early-stage power management methodology to be adopted within the MPEG-RVC context. Starting from different high-level specifications, our mapping methodology identifies directly on the high-level models disjointed homogeneous logic clock regions, where the platform resources can be enabled/disabled together without affecting the overall system performance. To extend its usability to the RVC community, we have integrated this methodology within the Multi-Dataflow Composer (MDC) tool. MDC is a tool for on-the-fly reconfigurable signal processing platforms deployment. In this paper, we extended MDC to address power-aware multi-context systems. To prove the effectiveness of our work, a coprocessor for image and video processing acceleration has been assembled. This latter has been synthesized on a 90 nm ASIC technology, where demonstrated up to 90 % of reduction in the dynamic power consumption on different dataflow-intensive applications. The coprocessor has been implemented also on FPGA, confirming, partially, the benefits of adopting the proposed methodology
Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design
No full textComplexity management, portability and long term adaptivity are common challenges in different fields of embedded systems, normally colliding with the needs of efficient resource utilization and power balance. Image/signal processing systems, though required to offer a large variety of complex functions, have also to deal with battery-life limitations. Wearable signal processing systems, for example, should provide high performance and support new generation standards without compromising their portability and their long-term usability. These constraints challenge hardware designers: early stage trade-off analysis and power management automated techniques are helpful to guarantee a reasonable time-to-market. In the field of video codec specifications, the MPEG standard known as Reconfigurable Video Coding (RVC) framework addresses functional complexity and adaptivity leveraging on the intrinsic modularity of the dataflow model of computation, but it still lacks in offering power management support. The main contribution of this work is providing an automatic early-stage power management methodology to be adopted within the MPEG-RVC context. Starting from different high-level specifications, our mapping methodology identifies directly on the high-level models disjointed homogeneous logic clock regions, where the platform resources can be enabled/disabled together without affecting the overall system performance. To extend its usability to the RVC community, we have integrated this methodology within the Multi-Dataflow Composer (MDC) tool. MDC is a tool for on-the-fly reconfigurable signal processing platforms deployment. In this paper, we extended MDC to address power-aware multi-context systems. To prove the effectiveness of our work, a coprocessor for image and video processing acceleration has been assembled. This latter has been synthesized on a 90 nm ASIC technology, where demonstrated up to 90 % of reduction in the dynamic power consumption on different dataflow-intensive applications. The coprocessor has been implemented also on FPGA, confirming, partially, the benefits of adopting the proposed methodology
Spectral Subband Centroids for Tone Vocoder Simulations of Cochlear Implants
No full textCochlear Implants (CIs) have long been used to partially restore hearing in profoundly deaf individuals through direct electrical stimulation of the auditory nerve. Changes in pitch due to electrode selection have been shown to conform to the tonotopic organisation of the cochlea; i.e., each electrode corresponds to a localised band of the human hearing spectrum. Studies have shown that it may be possible to produce intermediate place percepts in some patients by stimulating pairs of adjacent electrodes simultaneously. Tone vocoder simulations with 2-16 output channels were used to evaluate the effect of producing place cues similar to spectral subband centroids of each spectral analysis band. Signals were generated as a sum of sine waves positioned at the spectral subband centroid (rather than the usual centre frequency) of the frequency band relevant to each channel. Results showed improved vowel and consonant intelligibility, even with as low as 4-6 output channels.Griffith Sciences, Griffith School of EngineeringNo Full Tex
Reduction of Computational Amount in Person Verification Based on SVM Using Evoked Brain Wave by Ultrasound
Get PDFFor realizing continuous authentication of users, we have studied to use an electroencephalogram (EEG) evoked by ultrasound as biometrics. Users are presented only the ultrasound of their memorable music and verified whether genuine or not using the induced components of EEG. In our previous studies, the verification error rate of 0 % was achieved using multiple quantities in EEG as individual features and a support vector machine (SVM) as a verification method; however, it required a large amount of computation for processing SVM models. Thus, we reduce the number of SVM models by applying two selection methods of features and electrodes, which have been previously introduced. Furthermore, we examine the usage rates of features and electrodes in the reduced SVM models. By using only the electrodes with high usage rates, the verification error rate of 0 % is guaranteed with a small amount of computation
Handbook of signal processing systems
No full textHandbook of Signal Processing Systems is organized in three parts. The first part motivates representative applications that drive and apply state-of-the art methods for design and implementation of signal processing systems; the second part discusses architectures for implementing these applications; the third part focuses on compilers and simulation tools, describes models of computation and their associated design tools and methodologies. This handbook is an essential tool for professionals in many fields and researchers of all levels
An educational DSP platform based on a TMS320C5505 eZDSP
No full textWe developed a digital signal processor (DSP) platform that includes a box equipped with the C5505 eZdsp and easy to use software tools. This box includes a TMS320C5505 DSP, an audio interface, several communication interfaces, and a USB programming interface. Example applications show that the DSP platform is easy to use. This platform is developed by the Signal Processing Systems group at Eindhoven University of Technology and is used in DSP projects and education
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