1,722,276 research outputs found
sj-docx-1-jmk-10.1177_02761467221123918 - Supplemental material for A Goods-Dominant—Service-Dominant Perspective on Counterfeiting
No full textSupplemental material, sj-docx-1-jmk-10.1177_02761467221123918 for A Goods-Dominant—Service-Dominant Perspective on Counterfeiting by Sudeep Rohit and Kumar Rakesh Ranjan in Journal of Macromarketing</p
Frontiers in Mechanochemistry and Mechanical Alloying
Full text linkThe book Frontiers in Mechanochemistry and Mechanical Alloying [ISBN : 97881-87053-69-8] (Rakesh Kumar, Srinivasan Srikanth and Surya Pratap Mehrotra (Eds.))is a compilation of papers presented in the VI International Conference on Mechanochemistry and Mechanical Alloying (INCOME) held at CSIR-National Metallurgical Laboratory (CSIR-NML), Jamshedpur (India) during December 1-4,2008 under the aegis of International Mechanochemistry Association (IMA). Fifty three papers (334 pp) included in this book are written by experts from all over the world
Pharmacological Evaluation of the D2 and D3 Dopamine Receptor Selective Compounds on L-Dopa Dependent Abnormal Involuntary Movements in Rats
No full textKumar Rakesh, Pharmacological Evaluation of the D2 and D3 Dopamine Receptor Selective Compounds on L-dopa Dependent Abnormal Involuntary Movements in Rats. Master of Science (Pharmacology & Neuroscience), May 2008, 106 pp, 21 illustrations, references, 31 titles. Parkinson’s Disease (PD) is a progressive, neurodegenerative disease of the dopamine neurons that innervate the striatum and is characterized by resting tremor, rigidity, bardykinesia and postural instability. L-dopa treatment is the most common and effective therapy for PD. However, both motor (wear-off phenomena, rigidity and dyskinesia) and non-motor (sweating, tachycardia, restless leg syndrome, anxiety, depression, confusion, reduced alertness, psychosis and/or dementia) side effects are associated with long term L-dopa therapy. Motor complications depend on the duration of L-dopa treatment and the abnormal involuntary movements are known as L-dopa-induced dyskinesia (LID). Several studies have suggested a possible role of the dopamine D3 receptor subtype in LID. Here I evaluated the effects of various D2 and D3 dopamine receptor selective compounds on LID in 6-hydroxydopamine-induced complete lesioned hemi-parkinsonian model of rat. D3 dopamine receptor selective compounds (agonists, partial agonists or antagonists) have antidyskinetic effects on LID. Co-administration of D3 dopamine receptor agonist and D3 dopamine receptor antagonist has additive effects in attenuating the LID instead of antagonizing the effects of each other in vivo. D3 dopamine receptor selective compounds attenuated apomorphine-induced dyskinesia
Use of combustion synthesis/self-propagating high-temperature synthesis (SHS) for the joining of similar/dissimilar materials
No full textAnalyzing and Optimizing Serverless Function Execution
Full text linkServerless computing, implemented as Function-as-a-Service (FaaS), is an emerging and rapidly growing cloud computing model. It attracts users thanks to its simple and flexible programming model, fine-grained billing model, and zero resource-provisioning overhead for the developer. In FaaS, the fundamental unit of computation is a function, defined as a stateless unit of code executed on-demand when triggered by an external event such as an HTTP request. To enable code reuse, FaaS functions are normally small with well-defined purpose and therefore they have a very short execution time, often less than a second. Larger FaaS applications are built by composing multiple individual functions. To communicate, the functions often use high-latency network-backed Remote Procedure Calls (RPC) interfaces. This adds significant overhead to FaaS application execution, especially as the number of functions in an application increases and the communication latencies compound. The short execution time, transient resource allocation, and high communication overhead raise the question of how to build hardware and software platforms for efficiently executing FaaS applications. This thesis addresses this question from two research directions.
The first research direction investigates the hardware perspective of serverless computing. To that end, we first examine the impact of the short execution time of FaaS functions on microarchitectural structures.The driving hypothesis is that, since FaaS functions run for a very short time, they do not give microarchitectural structures enough time to warm up sufficiently to perform optimally. Primarily, our analysis finds that the hypothesis holds only for functions with an extremely short execution time (<1 ms). Our analysis additionally finds that FaaS functions have large instruction working sets. This finding means that FaaS functions are affected by the widely established front-end bottleneck problem. This problem is caused by large instruction working sets overwhelming the capacities of the branch target buffer (BTB) and instruction caches of processors. A long line of research has established that instruction cache prefetching is an effective way to alleviate the frontend bottleneck. Fetch-directed instruction prefetching (FDIP) is a particularly attractive class of such instruction prefetchers. However, for FDIP to be effective it requires a sufficiently large BTB. However, access latency, area, and power constraints preclude simply increasing the size of a conventionally designed BTB.Therefore, to increase BTB storage density, we introduce BTB-X, an optimized BTB organization based on the critical observation that branch target offset lengths are unevenly distributed in server workloads.Therefore, BTB-X offers entries with different storage capacities to accommodate the offset size variance. BTB-X stores 2.24× more branches than a conventional BTB and 1.3× more branches than the state-of-the-art storage-optimized BTB design.
Following the second research direction, we focus on the software aspect of efficiently executing FaaS functions. One of the most significant overheads in FaaS function execution is the excessive latency of the network-backed RPC interfaces often used for inter-function communication. Previous proposals aiming to alleviate this communication latency are unattractive since they sacrifice at least one of the essential properties of FaaS that makes the programming model appealing. To address this, we introduce CoFaaS, a fully automated software-based transformation for FaaS functions that does not sacrifice any of FaaS’ essential properties. We observe that for functions written in different languages to communicate, the RPC interfaces exposed by each function must be well-defined. The critical insight exploited by CoFaaS is that these well-defined interfaces allow us to transform the implementation code of a function freely as long as its external interface is kept unchanged. This allows CoFaaS to retarget the FaaS functions comprising a FaaS application to run on a single WebAssembly runtime. By doing this, CoFaaS alleviates the inter-function communication overhead. CoFaaS reduces the application round-trip time by up to 6× and the inter-function communication and inter-function communication time by up to 100×
Architectural exploration of Si-IF many-die processors
Full text linkEmbargo set by: Seth Robbins for item 107443
Lift date: 2020-09-04T20:50:11Z
Reason: Author requested closed access (OA after 2yrs) in Vireo ETD systemOpen Restriction set for Item 107443 on 2019-05-09T15:52:26Z with date null by [email protected] Restriction set for Item 107443 on 2019-05-09T15:52:28Z with date null by [email protected], single-die processors dominate today’s computing landscape. High performance systems achieve massive throughput by connecting large numbers of discrete chips – CPUs, GPUs, FPGAs – through high latency, low bandwidth interconnects. However, such systems provide limited performance scaling due to high communication costs between the discrete chips. This thesis proposes an alternate path for performance scaling: integrating many dies onto a single chip using a novel assembly technology – Silicon Interconnect Fabric (Si-IF). Many-die processors have both a technical and an economic advantage over their monolithic counterparts. We demonstrate potential benefits of a many-die approach using two approaches: efficient workload coverage design space exploration using many dies and evaluating a many-die wafer-scale GPU design.Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2020-05-01The student, Daniel Petrisko, accepted the attached license on 2018-04-24 at 12:27.The student, Daniel Petrisko, submitted this Thesis for approval on 2018-04-24 at 12:41.This Thesis was approved for publication on 2018-04-25 at 08:30.DSpace SAF Submission Ingestion Package generated from Vireo submission #12382 on 2018-08-31 at 17:30:09Made available in DSpace on 2018-09-04T20:47:27Z (GMT). No. of bitstreams: 3
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Previous issue date: 2018-04-25Embargo set by: Seth Robbins for item 107443
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K-hot pipelining
Full text linkComputing systems in almost every application domain now support techniques to trade off power and performance. Such techniques are used to enforce power and thermal constraints, manage power and thermal budgets and respond to temperature and aging. Unfortunately, many of the current techniques are limited in the dynamic range they provide and scale poorly with technology. Techniques that can supplement or replace current techniques are needed. We propose k-hot pipelining, a novel technique to support multiple power-performance points in a processor. The key idea is to provide power and clock to only k stages of an m-stage pipeline (k < m); the k stages to be powered on change as instructions flow through the pipeline. Since the remaining m − k stages do not consume power, the technique results in power savings at the expense of performance. k-hot pipelining can be software or hardware-controlled, workload-agnostic or workload-adaptive, and can be used to provide power-performance points not supported by existing techniques. For one implementation of k-hot pipelining, we show that up to 49.9% power reduction is possible over the baseline design. Power reduction is up to 47% over the lowest power point supported by DVFS.Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2018-08-01The student, Dao Lu, accepted the attached license on 2016-07-05 at 16:46.The student, Dao Lu, submitted this Thesis for approval on 2016-07-05 at 16:50.This Thesis was approved for publication on 2016-07-06 at 14:10.DSpace SAF Submission Ingestion Package generated from Vireo submission #9764 on 2016-11-10 at 12:24:54Made available in DSpace on 2016-11-10T18:39:17Z (GMT). No. of bitstreams: 2
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Previous issue date: 2016-07-06Embargo set by: Seth Robbins for item 95454
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Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD systemEmbargo set by: Seth Robbins for item 95454
Lift date: 2018-11-10T18:43:22Z
Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD systemU of I Only Restriction Lifted for Item 95454 on 2018-11-11T10:15:28Z
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Performance analysis of machine learning applications on rapid: a highly parallel computer architecture
Full text linkOver the past few years, the interest and application of machine learning algorithms has risen exponentially. Machine learning has found extensive use in diverse fields like self-driving cars, speech recognition, image processing, computer vision, molecular biology, security etc. A lot of recent research involves evaluation of machine learning applications on different architectures. In this thesis, we evaluate the performance of six common machine learning algorithms: K-Means, K-Nearest Neighbors, Linear Regression, Latent Dirichlet Allocation, Deep Neural Network, and Radix Sort on RAPID. RAPID is a highly parallel computer architecture developed at Oracle Labs for accelerating and improving the performance of database analytic workloads. We find that the RAPID platform performs well on the performance-per-watt metric i.e. it is a power-efficient architecture. Moreover, the machine learning applications can be easily scaled to hundreds of nodes of the RAPID architecture, thereby making it suitable for distributed machine learning applications. However, we find certain bottlenecks in the micro-architecture, memory system and network of the RAPID architecture and propose optimizations to make it a more performance efficient architecture for machine learning applications.Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2019-05-01The student, Aakash Modi, accepted the attached license on 2017-04-26 at 12:22.The student, Aakash Modi, submitted this Thesis for approval on 2017-04-26 at 12:30.This Thesis was approved for publication on 2017-04-26 at 16:22.DSpace SAF Submission Ingestion Package generated from Vireo submission #11087 on 2017-08-10 at 14:32:41Made available in DSpace on 2017-08-10T19:52:24Z (GMT). No. of bitstreams: 2
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Previous issue date: 2017-04-26Embargo set by: Colleen Fallaw for item 102690
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