239 research outputs found
Sort by
Self-Timed VLSI Systems
No full textThis short paper is intended to explain why the subject of self-timed logic is relevant to a conference on VLSI.
Scaling down feature size and scaling up chip area not only increases the complexity of chips, but also changes relationships in the parameters which describe the physical characteristics of switching devices, circuits,
and wires. The physical change which most impacts the design disciplines employed for VLSI -- particularly the timing aspect of design -- is the increased
wire delay associated with the increased resistivity of scaled down wires. Wires that run even a small fraction of the way across a chip will impose a significant delay. Clock distribution and long-distance communication
required by synchronous systems will become problematic. Otherwise, it appears that the timing aspect of design for submicron feature size circuits
will generally resemble that of today's MOS technology, in that delays will be largely determined by parasitic wiring capacitance
Storage Management in a LISP-based Microprocessor
No full textWe present a design for a class of computers whose "instruction sets" are based on LISP. LISP, like traditional stored-program machine languages
and unlike most high-level languages, conceptually stores programs and data in the same way and explicitly allows programs to be manipulated as data. LISP
is therefore a suitable language around which to design a stored-program computer architecture. LISP differs from traditional machine languages in that the program/data storage is conceptually an unordered set of linked
record structures of various sizes, rather than an ordered, indexable vector or integers or bit fields of fixed size. The record structures can be organized into trees or graphs. An instruction set can be designed for
programs expressed as such trees. A processor can interpret these trees in a recursive fashion, and provide autoaatic storage management for the record
structures.
We concentrate here on the issues of memory management in such a computer, and the reasons why a layered design strategy is not only desirable and natural but even mandatory.
A prototype VLSI LISP microprocessor has been designed and fabricated for testing. It is a small-scale version of the ideas presented here, containing a sufficiently complete instruction interpreter to execute small programs, and a rudimentary storage allocator. We intend to design and
fabricate a full-scale VLSI version of this architecture in 1979
Implementing VLSI Systems in a Research Environment
No full textTraditionally, integrated circuits have been designed and implemented only for applications likely to require large numbers of chips. The IC's were realized by closely cooperating experts, each well-versed in some
aspect of the art of integrated circuit design and manufacturing. Economics and the detailed knowledge needed prohibited any group unwilling or unable to make a considerable resource commitment from producing
integrated circuits. Prototypes and one- or few-of-a-kind systems were built from off-the-shelf components (or not at all}. Recently, advances in IC technology and the emergence of new design methodologies have made it
possible for people lacking IC manufacturing expertise to design VLSI circuits. While the population able to cast their ideas in silicon is increasing, a previously unseen set of problems has emerged. The remainder
of this paper will examine the background of these people and some of the problems that are now critical obstructions in the path to implementing VLSI circuit designs
Silicon Compilation - A Hierarchical Use of PLAs
No full textThis paper proposes a way to compile a silicon layout directly from synchronous logic specification. The motivation for introducing compilation into the silicon world comes from its extreme success in the software world. As we see silicon area increasing and circuit complexity
increasing, we might feel much in common with the early day programmers who faced increasing memory availability along with increasing program complexity
Hierarchical Design for VLSI: Problems and Advantages
No full textThis paper describes the hierarchical design process for
VLSI circuits and discusses the potential benefits and
disadvantages
Logic-Enhanced Memories: An Overview and Some Examples of Their Application to a Radar Tracking Problem
No full text[none
VLSI Design Methodology: The Problem of the 80's for Microprocessor Design
No full textThe rapid evolution of semiconductor technology
continues to make possible increasingly sophisticated
electronic systems on single chips of
silicon. By 1982, a single silicon chip is projected
to have well over 100,000 transistors.
This level of complexity represents a major
problem for the VLSI designer in the 1980's.
Unless there is a major change in design
methodology, this level of VLSI technology will
be grossly under-utilized due to the problems of
design, layout and checking. With present design
methods, a 100,000 transistor MOS chip will take
60 man years to layout and another 60 man years
to debug
The Trimosbus
No full textThis paper describes a family of communication buses that
permit individual senders to communicate with an arbitrary number of receivers and to wait for the last receiver to respond. TRI in the name signifies the use of three wires for sequencing. The bus is speed-independent in that no assumptions about the relative or absolute speed with which bus participants respond to bus signals are required to ensure proper sequencing of bus operations.
Data are passed by two separate mechanisms. First, during
normal bus operation a number of parallel data wires are used to transmit individual characters or numbers. The MOS part of the name refers to the fact that the high input impedance of MOS circuits permits us to use these data wires themselves as storage nodes. Second, for debugging, testing, and error recovery a slower serial data path is provided.
This paper also describes a TRIMOSBUS message protocol.
The protocol uses sequences of bus cycles to transmit messages of arbitrary length. The unique sender can be selected either on a message by message basis by arbitration, or within a message by mutual consent. We plan to use the TRIMOSBUS and this message protocol in a variety of system designs at Caltech, Carnegie-Mellon University and Washington University