239 research outputs found
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Data Base Considerations for VLSI
No full textThis paper will discuss the motivations and history of data base design for design automation. The objectives of using a data base for VLSI design are outlined and the aspects of merging the logical and physical data for a VLSI design are proposed. A hierarchical data base structure and model is presented and typical data examples of logical and physical VLSI data are mapped into this structure
Characterization and Scaling of MOS Flip Flop Performance in Synchronizer Applications
No full textThe measured and calculated values of t he Flip Flop parameters needed to specify synchronizer reliability are presented for 3 different depletion-load,
silicon gate, NMOS, R-S Flip Flop circuits with gate lengths ranging from 6μm to 4.2μm. Estimates of the probability of synchronizer failure to resolve within allowed or desired times can be determined from these
parameters
Bristle Blocks: A Silicon Compiler
No full textStandard LSI Design Automation systems are database management systems that aid the circuit designer by organizing the collection of submodules that comprise a chip. This type of file system
usually does not aid in the actual computation of silicon layout, and can hinder a designer with program constraints that have little or nothing to do with silicon constraints. The Bristle Block system is an attempt to create a silicon compiler that will perform the majority of the implementation computation while placing a minimum set of constraints on the designer. The goal of the Bristle
Block system is to produce an entire LSI mask set from a single page, high level description of the
integrated circuit
Synchronization Strategies
No full textComputing systems are now frequently composed of independently clocked subsystems that cooperate to perform the function desired for the whole. This type of architecture has many advantages and promises to be the standard for the forseeable future. With the trend towards more and more gates per chip, the number of chips per subsystem gets smaller and smaller, and we can expect to soon see one or more subsystems per chip. This transition
will require contributions from disciplines previously outside the field of chip design, and every issue will have to be carefully worked out beforehand because debugging chips of this complexity is a difficult and costly task.
This paper addresses one of those issues - the design of reliable synchronization logic for interfacing independently clocked subsystems. The design of this logic is not a normal exercise in clocked logic design
because the operating environment is such that the response times of some flipflops will be unbounded, and an improper appreciation of this phenomenon can result in designs plagued by intermittent synchronization failures . The
absence of a bound has been documented in the literature, but only from an experimental and analytic standpoint, and no generally applicable methodology for dealing with it has been suggested. As a result, it is not common knowledge
among logic designers, and future systems are liable to suffer from it. The objective of this paper is to assist the logic designer by reviewing the basic phenomenon, characterizing it quantitatively, and presenting techniques
for coping with it
Object Oriented Raster Displays
No full textThis paper describes a special-purpose MOS/LSI memory device and its design. This device was designed as an attempt to speed up the display and animation of multicolor raster display images, and is highly specialized to that task. Generalizations of the approach taken would be suitable, and possibly economical for geometrical computations encountered in the course of manipulating integrated circuit layouts, such as design rule checking. These generalizations will be discussed as will the design and implementation of this particular chip
Area-Time Complexity for VLSI
No full textThe complexity of the Discrete Fourier Transform (DFT) is studied with respect to a new model of computation appropriate to VLSI technology. This model focuses on two
key parameters, the amount of silicon area and time required to implement a DFT on a single chip. Lower bounds on area (A) and time (T) are related to the number of points
(N) in the DFT: AT^2 > N^2/16. This inequality holds for any chip design based on any algorithm, and is nearly tight when T = Θ(N^(l/2)) or T = Θ(log N)
Submicron Fabrication
No full textSubmicron fabrication is the broad interdisciplinary
activity that produces microstructures with feature
sizes less than one micrometer. Much has been published
on the fabrication of custom integrated circuits using
advance lithography and pattern transfer techniques.
This talk reviewed some of the limit at ions and advantages
of submicron fabrication. Also a brief summary of the
objectives, equipment status and accomplishments of the
new National Submicron Facility at Cornell University were
discussed
Requirements for a Research-oriented IC Design System
No full textComputer-aided design techniques for integrated circuits grown in an incremental way, responding to various perceived needs, so that today there are a number of useful programs for logic generation, simulation at various levels, test preparation, artwork generation and
analysis (including design rule checking), and interactive graphical editing. While the design of many circuits has benefitted from these programs, when industry wants to produce a high-volume part, the design and layout are done manually, followed by digitizing and
perhaps some graphic editing before it is converted to pattern generation format, leading to the often heard statement that computer-aided design of integrated circuits doesn't work. If progress is to be made, it seems clear that the entire design process has to be thought through in basic terms, and much more attention must
be paid to the way in which computational techniques can complement the designer's abilities. Currently, it is appropriate to try to characterize the design process in abstract terms, so that implementation and technological biases don't cloud the view of a desired system. In this paper, we briefly describe the conversion of
algorithms to masks at a very general level, and then describe several projects at MIT which aim to provide contributions to an integrated design system. It is emphasized that no complete system design exists
now at MIT, and that we believe that general design considerations must constantly be tested by building (and rebuilding) the various subcomponents, the structure of which is guided by our view of the overall design process
