239 research outputs found
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Single-Chip Computers, the New VLSI Building Blocks
No full textCurrent trends in the design of general purpose VLSI chips are analyzed to explore what a truly modular, general-purpose component for digital computing systems might look like in the mid 1980's. It is concluded that such a component would be a complete single-chip computer, in which the hardware for effective interprocessor communication has been designed with the architecture
of the overall multiprocessor system in mind. Computation and communication are handled by separate processors in such a manner, that both can be performed simultaneously with full efficiency.
This paper then describes relevant features of X-TREE, a research project which addresses the question how the power of VLSI of the next decade can best be used to build general purpose computing systems of arbitrary size. In
X-TREE, a general VLSI component realizable in the mid 1980's is defined, and its interconnection into a hierarchical tree-structured network is studied. The
overall architecture, communications issues and the blockdiagram of the modular component used are discussed
How to Use 1000 Registers
No full textThe advent of VLSI technology will allow the fabrication of complete computers plus memory on one chip. There will be an architectural challenge in the very near future to adjust to this trend by designing balanced architectures using hundreds or thousands of registers or other small blocks of memory. As the relative price of memory (vs. random logic) drops even further, the need for register-heavy architectures will become even more pronounced. In this paper, we discuss a spectrum of ways to exploit more registers in an architecture, ranging from programmer-managed cache (large numbers of explicitly-addressed registers, as in the Cray-1) to better schemes for automatically-managed cache. A combination of compiler and hardware techniques will be needed to maximize effective register use while minimizing transmission bandwidth between various memories. Discussed techniques include merging activation records at compile time, predictive cache loading, and "dribble-back" cache unloading
A Data-Drive Machine Architecture Suitable for VLSI Implementation
No full textA machine architecture is presented which is capable of supporting very high levels of concurrency. The machine language of the class of machines described here is a graphical program schema known as data-driven nets. The
machine architecture is arbitrarily extensible and consists of a recursively organized hierarchy of homogeneous processor-store modules. System control is decentralized, and each module is a completely asynchronous processing
site, capable of executing any machine language program. Resource allocation is performed dynamically on the basis of the amount of available concurrency in the program and on the availability of physical resources
A Subnanosecond LSI Family for Mainframe Technology
No full textA subnanosecond LSI family is defined for next generation mainframes. It employs distributed on-chip regulation to reduce system power supply cost, stacked structures for delay-power improvement, on-chip test/diagnostic monitors and signature circuits to improve system maintainability
WSI Distributed Logic Memories
No full textWafer-Scale Intearation (WSI) offers the possibility of departing from the von Naumann computer architecture and alleviating its implementation problems. By interconnecting the good chips on an undiced wafer, WSI provides a multiplicity of processing elements and bypasses the expensive stages of chip and printed circuit board
manufacture. Whereas VLSI offers low-cost components at the sub-system level, WSI offers low-cost computer systems . Hence, traditional market pressures deter the speculative development of a range of VLSI chips in order to launch a radically new computer structure. However, WSI
offers the integration of a new architecture in a single development
VLSI and High Performance Computers
No full textThis talk will outline three items concerned with the application of VLSI to high performance computing machines. These are:
1. Direction of VLSI and System Design Variables.
2. Systems Design Options.
3. Technological problems in building a VLSI machine.
Item one will summarize trends in bits per chip for memories and circuits per chip.
Item two will briefly review design options available to large system designs as a result of the forthcoming high degree of integration (i.e., improved mac hine organization, increased instruction concurrency, new subsystem concurrency).
Item three will outline some key VLSI technology problems
relevant to VLSI machine design. Examples are:
Pins, packaging and performance interactions;
switching noise and technology limitations;
design automation problems and requirements
Timing Considerations in Logic Arrays and Their Importance to Self Timed Digital Circuits
No full textThis paper presents a method for the design of self timed circuits on an integrated circuit that takes advantage of certain temporal constraints that are realizable in logic arrays.
This method of design recognizes two distinct environments for circuits, the local environment and the global environment and further recognizes that the assumptions regarding the temporal characteristics of the system that may be valid in the local environment may not be valid in the global environment.
This paper shows how self timed circuits can be systematically designed on a single chip using assumptions reasonable for components on a single chip.
This paper is based on our work on Structured Logic Arrays (SLAs) and first explains the intricacies of the temporal constraints implemented in the structured array and then shows how one can take advantage of these constraints in the design of self timed circuits. In this structure, for example, it is possible to design an asynchronous sequential state machine with non adjacent transitions without getting into hazardous conditions. What is presented is related to Petri nets and their realization in circuits.
The circuits that are designed using this method are very regular in structure and are efficient in utilization of chip area. Furthermore, fairly large integrated circuits can be designed relatively fast using this method. Examples of some chip designs are presented
Let's Design Algorithms for VLSI Systems
No full textVery Large Scale Integration (VLSI) technology offers the potential of implementing
complex algorithms directly in hardware [Mead and Conway 79). This paper (i) gives
examples of algorithms that we believe are suitable for VLSI implementation, (ii) provides a
taxonomy for algorithms based on their communication structures, and (iii) discusses some
of the insights that are beginning to emerge from our efforts in designing algorithms for
VLSI systems
A Simple Two-Layer Aluminum Metal Process for VLSI
No full textThe use of two levels of metal interconnect lines in an integrated circuit chip layout is a very desirable feature that allows higher density and greater freedom in the placement of the active components. In spite of these benefits it has often been avoided in the design of integrated circuits. For many applications the cost
of the extra processing steps is not justified. In the case of MOS technology, long diffusion runs can be successfully used. In silicon gate MOS the polycrystalline silicon itself provides, with some restrictions, a second level of signal interconnect lines. However other technologies, for example I^2L, need a second layer of low-resistance
metal interconnect to effectively utilize the chip area.
While conceptually simple, two-layer metal processes have proved to be quite difficult to implement. This paper describes a relatively simple two-layer metal process that is well suited to university laboratories and others with limited facilities