239 research outputs found
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Special Purpose Hardware for Design Rule Checking
No full textSpecial purpose hardware can significantly increase the speed of integrated circuit design rule checking. The architecture described in this paper uses four custom chips to implement a raster scan DRC algorithm. It allows the use of 45° angles and can be programmed to check a wide variety of design rules involving an arbitrary number of layers. A shrink/expand operation allows the use of rasterization grids that are small relative to the minimum feature size. Using the Mead/Conway NMOS design rules and assuming a grid size of 1/2λ or 1/4 the minimum transistor width, this hardware can completely check a 3000λx3000λ layout in under a minute, if the input data can be provided quickly enough
A VLSI Tactile Sensing Array Computer
No full textHere we describe a device that is at once a special purpose parallel computer and a high resolution tactile array sensor. We are interested in extending the technology that gives a robot manipulation system information about contact between the manipulator hand and its environment. We have replaced the passive substrates of earlier tactile sensors with a custom designed LSI device that handles transduction, computing, and communication. Large metal electrodes on the surface of the device are placed in contact with a conductive rubber. Deformations of this elastic material are sensed by measuring changes in its local resistivity. The sensory architecture eases the problem of connecting the transducer and computer by using an array of processors to filter and reduce raw data before communication. Since large arrays covering an entire intact wafer are planned, the design includes backup redundancy for the computing elements, and mechanisms for automatic replacement of failed elements
VLSI and Technological Innovation
No full textVLSI relies on a range of disciplines for its successful implementation. Two of the most important of these are still in their infant stages.
A. Design methodologies to manage complexity.
B. Architecture of ultra concurrent machines.
Innovation in infant disciplines occurs most rapidly and successfully when a large number of small groups proceed independently under the motivation of
market opportunity. In a few years, a substantial fraction of the engineering work force will have a working knowledge of LSI design. At the same time,
fabrication areas are becoming more and more capital intensive. What is needed is a clean, standard interface between a multitude of small diverse VLSI design
groups and a few state-of-the-art fabrication suppliers. A proposal for such an interface is presented in this article
A Cellular, Language Directed Computer Architecture
No full textIf a VLSI computer architecture is to influence the field
of computing in some major way, it must have attractive properties in all important aspects affecting the design, production, and the use of the resulting computers. A computer architecture that is believed to have such properties is briefly discussed
Direct VLSI Implementation of Combinatorial Algorithms
No full textWe present new algorithms for dynamic programming and transtivc closure which arc appropriate
for very large-scale integration implementation
A Computer Study of Electron-Electron Interaction in high Density Electron Beams
No full textHigh density electron beams are simulated by a computer, and the trajectory displacement and energy broadening caused by electron-electron interaction are investigated computationally. The results are summarized into two empirical formulas which represent dependences of
the average trajectory displacement and the average energy broadening on the beam parameters. The results show that the trajectory displacement caused by electron-electron interaction imposes a severe problem on
system designers using high density beams, and that energy broadening on the order of 1eV may well be attributed to electron-electron interaction. The method of simulation is also described
VLSI System for SAR Processing
No full textSynthetic Aperture Radar (SAR) is a radar system that processes the return signal to achieve the effect of having a larger aperture than the one provided by the physical dimensions of its antenna. The processing consists of a
weighted summation of regularly spaced samples from the signal history, hence of logic for the arithmetic and storage for the signal history. LSI and VLSI
technology offer some beautiful ways to implement this computation in chips in which the storage and logic functions are commingled.
The SAR problem discussed in this paper is based on actual requirements set forth by NASA for a spaceborne application.
The requirements for high resolution and high quality necessitate a data sampling rate of 7.5 MHz. For each data value 1,025 4-bit complex multiply+add operations are needed, which is equivalent to 7.7 GHz complex
multiply+add operation rate. Since this rate is much too high for general purpose systems, a special-purpose device was sought.
This paper discusses two architectures based on parallel operation of 1,025 identical cells, each of which is capable of performing arithmetic, storage, and several control operations. The operation rate in each device is only 7.5 MHz, which is quite manageable, especially with the help of a substantial degree of pipelining.
A computational-mathematical analysis is used as a primary tool for evaluating the design and some of its tradeoffs.
Two different approaches are discussed and compared; both are based on having 1,025 identical cells working in parallel, but differ in their dual approaches
to the flow of data. The mathematics require a relative motion of the data with respect to some (relatively) constant sets of coefficients. In one approach the coefficients are held stationary in space, and the data flows past them; in the other, the data is held and the coefficients flow past.
The paper discusses the architecture, both approaches, some of the control issues, and most important, some aspects of the methodology of the design
Systolic Priority Queues
No full textVery large scale integrated (VLSI) circuit technology has made it possible to build
multiprocessor hardware devices to aid in the rapid solution of sophisticated problems.
An algorithms designer wishing to take full advantage of the massive parallelism offered
by VLSI must address geometric issues hitherto relegated to layout artists. The reason
for this is that VLSI is a planar technology in which the interconnections among
components on a chip may cost more than the components themselves. The designer of a
multiprocessor algorithm to be implemented in this technology must consider the
complexity of the data paths between processors in evaluating the algorithm
Device and Circuit Design for VLSI
No full textA review of the device and circuit design complexity and limitations for VLSI is presented. VLSI device performance will be limited by second order device effects, interconnection line delay and current density and chip power dissipation. The complexity of VLSI circuit
design will require hierarchical structured design methodology with special consideration of testability and more emphasis on redundancy. New organizations of logic function architectures and smart memories
will evolve to take advantage of the topological properties of the VLSI silicon technology