239 research outputs found
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Towards More Realistic Models of Computation for VLSI
No full textWe propose two new models of computation for VLSI which take into consideration the physical nature of
information, the properties of wires. and the geometrical structure of the circuit. Both are refinements of the
Kung-Thompson model, and make the main additional assumption that the propagation time of information
is at best linear in the distance. The first is the more general and applies for any planar technology. It is in a
sense the minimal physical model. The second, more restrictive, is specially tailored for electrical
technologies. Our approach is motivated by the failure of previous models to allow for realistic asymptotic
analysis. For each model, we are able to show new lower bounds and trade-offs for many well-known problems
Two Timing Samplers
No full textTesting VLSl chips presents a variety of problems. some of which can be solved by building on-chip testing
structures. On-chip testing structures can allow a designer to test aspects of a circuit which might be difficult to
test even with expensive test equipment and moreover can provide reasonable testing hardware to designers who
do not have access to sophisticated off-chip testing equipment.
In this paper we describe a type of on-chip test structure called H timing sampler which enables the designer to
accurately measure when on-chip signal transitions occur. The timing samplers we present are simple. They
have been fabricated as part of a multi-project chip and experimental results show that they arc reasonably
accurate as well
Minimum Propagation Delays in VLSI
No full textWith feature sizes decreasing and chip area increasing it becomes more and more time consuming to transport signals over long distances across the chip [5]. Designers are already introducing more levels of metal connections,
using wider and thicker paths for longer distances. Another recent development is the introduction of an additional level of connections between the chip and the
pc-board, multilayer ceramic chip carriers. The trend is undoubtedly towards even more connecting levels.
In this paper we demonstrate that it is possible to achieve propagation delays that are logarithmic in the lengths of the wires, provided the connection pattern is designed to meet rather strong constraints. These constraints are, in
effect, satisfied only by connection patterns that exhibit a hierarchical structure. We also show that, even at the ultimate physical limits of the technology, the
propagation for reasonably sized VLSI chips is dominated by these considerations, rather than by the speed of light
Signal Delay in RC Tree Networks
No full textIn MOS integrated circuits, signals may propagate between stages with fanout. The exact calculation of signal delay through such networks is difficult. However, upper and lower bounds for delay that are computationally
simple are presented in this paper. The results can be used (1) to bound the delay, given the signal threshold; or (2) to bound the signal voltage, given a
delay time; or (3) to certify that a circuit is "fast enough", given both the maximum delay and the voltage threshold
Functional Verification in an Interactive Symbolic IC Design Environment
No full textThis paper describes verification techniques that have been implemented as part of
an interactive symbolic IC design system. Circuit analysis programs perform node
extraction and gate decomposition. They generate both transistor and gate level
circuit desriptions which are used as input to a transistor level digital MOS timing
simulator. The extraction programs make use of an intermediate circuit description
language which captures both geometric placement and circuit connectivity.
All programs are written in the C programming language and run under the UNIX
operating system. An example is included to demonstrate the operation of these
various techniques
MOSIS - The ARPA Silicon Broker
No full textThis paper is actually an edited transcript of the talk presented at the conference. Many references to visual accompaniments, difficult to reproduce here, have been eliminated
A One Transistor RAM for MPC Projects
No full textMany MPC projects, such as video frame buffers, need a large memory subsystem. A one transistor per bit dynamic memory using Mead-Conway design rules is being designed with this purpose in mind. The memory cell size is 16.5 λ by 8λ (about the same size as a 1975 4K RAM cell with λ = 2.5 microns).
While a complete high density memory subsystem has not been designed, two chips have been designed to test its major components. One chip is a 1K memory array that tests the sense amplifier, column decoder/driver, and read/write logic. This chip lacks a timing generator and clock drivers. The second chip tests some low power bootstrapped clock drivers. These test chips are currently being fabricated
Considerations for an Analog Four Quadrant SC Multiplier
No full textThis paper outlines the considerations and design of a four quadrant analog multiplier using switched capacitor (SC) techniques. The design algorithm for accomplishing the multiplication is described. Implementation of the algorithm is then presented. The predicted
accuracy of the multiplier is given and compared to preliminary breadboard
measurements. The multiplier described is presently being fabricated as an integrated circuit on a university multichip project using double-poly MOS technology
THE MPC ADVENTURES: Experiences with the Generation of VLSI Design and Implementation Methodologies
No full text[none
Bit-Serial Inner Product Processors in VLSI
No full textIn this paper we describe a bit-serial pipelined implementation of an inner product processor,
and related interconnections of a number of such processors on a single chip. We argue
that bit-serial computational models are particularly suited for VLSI, because of relatively inexpensive
communication links and arithmetic processing elements, in terms of the area occupied
on silicon. Sixteen inner product processors, described here, may be easily placed on a single
40-pin chip in today's NMOS technology with a 2 micron lambda. Similar arguments for bitserial
arithmetic were used in [3]. in a description of a design of a general purpose massively
parallel processor