239 research outputs found
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A Logic Design Theory for VLSI
No full textClassical switching theory fails to account for some key structural and logical properties of the transistor circuits used in VLSI design. This paper proposes a new logic design methodology called CSA theory which is suitable
for VLSI. Three kinds of primitive logic devices are defined: connectors (C), switches (S), and attenuators (A); the latter have the characteristics of pullup/pulldown components. It is shown that four new logic values
are required, in addition to the usual Boolean 0 and 1 values. These values introduce a concept of gain or drive capability into logic design; they also account for the high-impedance state of tri-state devices. The elements of
CSA theory and its application to some basic VLSI design problems are described. It is demonstrated that CSA theory provides a more powerful and more
rigorous replacement for the mixed logic/electronic methods currently used in VLSI design
A Structured Approach to VLSI Layout Design
No full textA new approach to the VLSI layout problem is proposed that produces a structured floor plan for an arbitrary network of interconnected processing elements. It is based on extracting a minimum spanning tree from a given representation of a computation network and using an efficient, structured layout scheme for this minimum spanning tree. Techniques to lay out trees as arrays of
layout slices are presented. It is assumed that the nodes of a network are identical in their layout size and connectivity. This method is valid at any level of a VLSI
design since these nodes may represent gates, cells or complex macros. An application of this approach to modified tree networks is described. Other useful applications of the method are mentioned
A Smart Memory Array Processor for Two Layer Path Finding
No full textThis paper describes three examples of hardware implementations of path finding schemes based on the Lee-Moore maze solving algorithm. one is purely a demonstration circuit to show the technique. The other two are complete LSI implementations which should be usable in building large and useful path finding machines. One of these two LSI circuits, known as the MAZER, is designed to find shortest paths from one point to another on a plane, where there is only one layer of allowable routes to take. As its name suggests, this chip solves ordinary mazes, or on a more practical level, it can route wires on a one sided printed circuit board. The other LSI circuit, known as the PATHFINDER, is designed to handle the two sided printed circuit board case. It finds a least costly path from one point to another where there are two parallel planes on which routes are allowed. Crossing of the path from one plane to another can be either unrestrcited, as in free via printed circuit boards, or permitted only in certain places, as in fixed via boards. The phrase "least costly" above can, for now, be read as "shortest", although in a later section a more general definition will be revealed.
The remainder of this document is divided into three parts. The first section outlines the original Lee-Moore algorithm for path finding on which the circuits described later are based. The second section details the one layer hardware, including both the demonstration circuit and the MAZER chip. Finally, the third section describes the PATHFINDER chip and the techniques used to conquer the problems encountered in two layer path finding. Documentation on the integrated circuits includes those results of testing and characterization which were available at the time of this writing
PLA Design in NAND Structure
No full textA NAND (serial gating) structure PLA of the MOS poly-silicon gate process has been developed for high density and medium fast speed VLSI application. Dynamic clocking is used for minimum power dissipation and
elimination of the ratio problem associated with static NAND gate. Ion-implantation for memory cell programming and the elimination of contact in the memory area drastically reduces the cell size, and reliability is improved .
A simple but effective self-timed clocking scheme is employed for better operating margins against process variations; the overhead chip area for the
clock generation is sufficiently small. The advantages of allowing metal signal and power lines to cross the PLA memory area is discussed. Some measured data
from a 3.5μm NMOS Si-gate process with regard to gate height and transistor sizes are also described
Electron Beam Testing and Restructuring of Integrated Circuits
No full textDramatic improvements in the cost, performance, and reliability of a digital system can he obtained if the system is integrated on a single chip. Many systems are sufficiently complex that the die size resulting from integration would be very large with a low probability of producing a perfect, functioning die. Since there is a real need for larger integrated systems than can be fabricated free of defects, it is likely that techniques which can
locate and "wire-around" defects will be useful and will allow the die-size to increase, perhaps to full-wafer size
The Rolf of Test Chips in Coordinating Logic and Circuit Design and Layout Aids for VLSI
No full textThis paper emphasizes the need for multipurpose test chips and comprehensive procedures for use in supplying accurate input data to both logic and circuit simulators and chip layout aids. It is shown that the location of test structures within test chips is critical in obtaining representative data, because geometrical distortions introduced during the photomasking process can lead to
significant intrachip parameter variations. In order to transfer test chip designs quickly, accurately, and economically, a commonly accepted portable chip layout notation and commonly accepted parametric tester language are needed. In order to measure test chips more accurately and more rapidly, parametric testers with improved architecture need to be developed in conjunction with
innovative test structures with on-chip signal conditioning
Communication in a Tree Machine
No full textCommunication assumes a progressively dominant and limiting role in VLSI because it becomes relatively more expensive in chip area, signal energy, and time.
The principle of locality becomes alI important to integrated systems design, and implies that larger single processors are not the route to performance improvements.
One computer architecture that can exploit the capabilities of VLSI is an ensemble of small processors operating concurrently.
The tree machine is such a structure. Each of the many processors in the binary tree can communicate directly only with its parent and two children. However,
the tree is programmed as if each processor had an arbitrary number of descendents, and the programs are compiled into code for a binary tree. We describe
the communication structure of tree machine programs, the compilation process, and the underlying hardware
Trends in Silicon Processing
No full textThe advent of very large scale integration will require
substantial progress in all aspects of silicon technology:
processing, lithography, modeling, design tools, chip architecture, and applications This paper will survey current trends in silicon integrated circuit fabrication, focusing on new developments and outstanding problems. Progress in both bipolar and MOSFET technologies will be considered. Silicon fabrication techniques will be described in terms of the repetitious application of operations that are additive (oxidation, doping, deposition), selective (lithography), and
subtractive (etching). The objective of these operations is a reliable and predictable device structure. Device structures will be described in terms of isolation areas, devices, contacts (intraconnection vias), wiring (interconnection lines), and passivation. Immediate problems in isolation size, device performance, contact resistance, and wiring topography will be identified. Future needs for improved structures will be indicated. Promising new approaches such as lightly-doped
drain FETs and silicide-on-polysilicon (polycide) wiring
will be described. Throughout this discussion the importance
of process modeling will be emphasized
A Notation for Designing Restoring Logic Circuitry in CMOS
No full textWe introduce a programming notation in which every syntactically correct program specifies a restoring logic component, i.e., a component
whose outputs are permanently connected, via "not too many" transistors, to the power supply. It is shown how the specified components can be translated into transistor diagrams for CMOS integrated circuits . As
these components are designed as strict hierarchies, it is hoped that the translation of the transistor diagrams into layouts for integrated circuits can be accomplished mechanically