239 research outputs found
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Towards a Formal Treatment of VLSI Arrays
No full textThis paper presents a formalism for describing the behavior of computational networks at the
algorithmic level. It establishes a direct correspondence between the mathematical expressions
defining a function and the computational networks which compute that function. By formally
manipulating the symbolic expressions that define a function, it is possible to obtain different
networks that compute the function. From this mathematical description of a network, one can
directly determine certain important characteristics of computational networks, such as
computational rate, performance and communication requirements. The use of this formalism for
design and verification is demonstrated on computational networks for Finite Impulse Response (FIR}
filters, matrix operations, and the Discrete Fourier Transform (DFT).
The progression of computations can often be modeled by wave fronts in an illuminating way. The
formalism supports this model. A computational network can be viewed in an abstract form that can
be represented as a graph. The duality between the graph representation and the mathematical
expressions is briefly introduced
A Methodology for Improved Verification of VLSI Designs without Loss of Area
No full textThis paper describes an IC layout methodology based on arbitrary outline cells, prevention of overlap, and mixed programs and graphics. Advantages
are: no loss in area over hand packing; incremental checking of design rules, component interconnection, and timing; reduction of visible complexity; and easy implementation. Disadvantages are: possible
proliferation of cell types and poor handling of cells with contacts not on the boundary. An implementation that uses and enforces this methodology is discussed
A Restructurable Integrated Circuit for Implementing Programmable Digital Systems
No full textThe Restructurable Integrated Circuit, a highly flexible and programmable multimicrocomputer is presented. The goal of this integrated circuit is to apply the large number of gates that are available on a custom designed VLSI
IC to the design of a highly flexible integrated circuit . The main application of the Restructurable Integrated Circuit (RIC) will be the implementation of digital system hardware through programmation of a RIC. The
flexibility provided within the RIC includes: user definable micro language, user programmable assembly language, user programmable microcode, dynamic
coordination of multiple internal processors, coordination of processors on multiple RICs, internal memory use as caches or as a member of a virtual memory hierarchy, qeneral topology for interchip communication and external
data paths, and a user definable interrupt mechanism. By providing this high degree of flexibility, the cost and reliability advantages of high volume
production can be accrued, while providing performance comparable to a custom VLSI IC
Communications for Next Generation single chip computers
No full textIt is the thesis of this report that much of what is presently thought to require specialized VLSI functions might instead be achieved by combinations of fast general purpose single chip computers with upgraded communication facilities. To this end, the characteristics of applications
of this nature are first surveyed briefly and some working principles established. In the light of these, three different chip philosophies are explored in some detail. This study shows that some upgrading of typical
single chip I/O will definitely be necessary, but that this upgrading does not have to be complex and that true multiprocessor-multibus operation could be achieved without excessive cost
SLIM: A Language for Microcode Description and Simulation in VLSI
No full textSLIM (Stanford Language for Implementing Microcode) is a programming language based system for
specifying and simulating microcode in a VLSI chip. The language is oriented towards PLA
implementations of microcoded machines using either a microprogram counter or a finite state
machine. The system supports simulation of the microcode and will drive a PLA layout program to
automatically create the PLA
Architecture for VLSI Design of Ree-Solomon Encoders
No full textIn this paper, the logic structure of a universal VLSI chip called the symbol-slice Reed-Solomon (RS) encoder chip is presented. An RS encoder can be constructed by cascading and properly interconnecting a group of such VLSI
chips. As a design example, it is shown that a (255,223) RS encoder requiring around 40 discrete CMOS IC's may be replaced by an RS encoder consisting of four identical interconnected VLSI RS encoder chips. Besides the size advantage, the VLSI RS encoder also has the potential advantages of requiring
less power and having a higher reliability
A Multiproject Chip Approach to the Teaching of Analog MOS LSI and VLSI
No full textMultiproject chip implementation has been used in teaching analog MOS circuit design. After having worked with computer simulation and layout aids in homework problems, students designed novel circuits including several high
performance op amps, an A/D converter, a switched capacitor filter, a 1 K dynamic RAM, and a variety of less conventional MOS circuits such as a VII converter, an AC/DC converter, an AM radio receiver, a digitally-controlled
analog signal processor, and on-chip circuitry for measuring transistor capacitances. These circuits were laid out as part of an NMOS multiproject chip. Several of the designs exhibit a considerable degree of innovation;
fabrication pending, computer simulation shows that some may be pushing the state of the art. Several designs are of interest to digital designers; in fact, the course has provided knowledge and technique needed for detailed
digital circuit design at the gate level
Algorithmic Layout of Gate Macros
No full textThis paper describes the basic modules of a gate-to-silicon compiler which accepts as its input a high level description of gate macros and generates a layout that satisfies particular technology (NMOS, for
example) and environmental parameters (layout area or time delay, for example)
The Torus: An Exercise in Constructing a Processing Surface
No full textA "Processing Surface" is defined as a large, dense, and
regular arrangement of processor and storage modules on a two-dimensional surface, e.g. a VLSI chip. A general method is described for distributing parallel recursive computations over such a surface. Scope rules enforcing
the "locality" of variables and procedure parameters are introduced in the programming language. These rules and a particular interconnection of the modules on the surface make it possible to transmit parameter and variable
values between modules without using extraneous communication actions.
The choice of the Processing Surface topology for binary recursive computations is discussed and a torus-like topology is chosen