International Journal of Reconfigurable and Embedded Systems (IJRES)
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Design of Mesh and Torus Topologies for Network-On-Chip Application
Get PDFNetwork-on-Chip (NoC) is a general purpose on-chip communication concept that offers high throughput, which is the basic requirement to deal with complexity of modern systems. In Network on chip topology design is one of the significant factors that affect the net delay of the system. In this paper mesh topology and torus topology are compared in terms of network delay for a given NOC application using Xillinc 9.1c
An Efficient Implementation of the Entire Transforms in the H.264/AVC Encoder using VHDL
Get PDFThe H.264/AVC standard achieves remarkable higher compression performance than the previous MPEG and H.26X standards. One of the computationally intensive units in the MPEG and H.26X video coding families is the Discrete Cosine Transform (DCT). In this paper, we propose an efficient implementation of the DCT, inverse DCTs and the Hadamard transforms in the H.264/AVC encoder using VHDL. The synthesis results indicate that our implementation of the entire transforms achieves lower power, delay and area consumption compared to the existing architectures in the H.264/AVC encoder
New Schmitt Trigger with Controllable Hysteresis using Dual Control Gate-Floating Gate Transistor (DCG-FGT)
Get PDFThis paper presents different low voltage adjustable CMOS Schmitt trigger using DCG-FGT transistor. Simple circuits are introduced to provide flexibility to program the hysteresic threshold in this paper. The hysteresis can be controlled accurately at a large voltage range. The proposed Schmitt trigger have been designed using 90nm 1.2V CMOS technology and simulated using Eldo with PSP device models. The simulation results show rail-to-rail operation and adjustable switching voltages VTH- (low switching voltage) and VTH+ (high switching voltage)
Design and Development of Stream Processor Architecture for GPU Application Using Reconfigurable Computing
Get PDFGraphical Processing Units (GPUs) have become an integral part of today’s mainstream computing systems. They are also being used as reprogrammable General Purpose GPUs (GP-GPUs) to perform complex scientific computations. Reconfigurability is an attractive approach to embedded systems allowing hardware level modification. Hence, there is a high demand for GPU designs based on reconfigurable hardware. Stream processor consists of clusters of functional units which provide a bandwidth hierarchy, supporting hundreds of arithmetic units. The arithmetic cluster units are designed to exploit instruction level parallelism and subword parallelism within a cluster and data parallelism across the clusters.For decreasing the area and power, a single controller is used to control data flow between clusters and between host processor and GPU. The designed of stream processor unit has been carried out in Verilog on Altera Quartus II and simulated using ModelSim tools. The functionality of the modelled blocks is verified using test inputs in the simulator.The simulated execution time of 8-bit pipelined multiplier is 60 ps and 100 ns for 8-bit pipelined adder while operating at 90 MHz
FPGA Based Embedded System Development for Rolling Bearings Fault Detection of Induction Motor
Get PDFBearing fault diagnosis is crucial in condition monitoring of any rotating machine. Early fault detection in machines can save millions of dollars in maintenance cost. Different methods are used for fault analysis such as short time Fourier transforms (STFT), Wavelet analysis (WA), Model based analysis, cepstrum analysis etc. Recently, there have been outstanding technological developments related to digital systems, in both hardware and software. These innovations enable the development of new designing methodologies that aim to the ease the future modifications, upgrades and expansions of the system. This paper presents a study of rolling bearing fault diagnosis of induction motor based on reconfigurable logic. A case study using FPGA, its design, as well as its implementation and testing, are presented
FPGA Implementation of Park-Miller Algorithm to Generate Sequence of 32-Bit Pseudo Random Key for Encryption and Decryption of Plain Text
Get PDFThere are many problems arises in randomized algorithms whose solutions are fundamentally based on assumptions that pure random numbers exist, so pseudo-random number generators can imitate randomness sufficiently well for most applications. The proposed scheme is a FPGA implementation of Park-Miller Algorithm for generating sequence of Pseudo-Random keys. The properties like High speed, low power and flexibility of designed PRNG(Pseudo Random Number Generator) makes any digital circuit faster and smaller. The algorithm uses a PRNG Module, it contains 32-bit Booth Multiplier, 32-bit Floating point divider and a FSM module. After generating a sequence of 32-bit Pseudo-Random numbers we have used these numbers as a key to Encrypt 128-bit plain text to become a cipher text and by using the same key to decrypt the encrypted data to get original Plain text. The Programming is done in Verilog-HDL, successfully synthesized and implemented in XILINX Spartan 3E FPGA kit
Configurable Router Design for Dynamically Reconfigurable Systems based on the SoCWire NoC
Get PDFNew Field Programmable Gate Arrays (FPGAs) are capable of implementing complete multi-core System-on-Chip (SoC) with the possibility of modifying the hardware configuration at run-time with partial dynamic reconfiguration. The usage of a soft reconfigurable Network-on-Chip (NoC) to connect these cores is investigated in this paper. We have used a standard switch developed with the objective of supporting dynamically reconfigurable FPGAs as the starting point to create a novel configurable router. The configurable router uses distributed routing suitable for regular topologies and can vary the number of local ports and communication ports to build multi dimensional networks (i.e., 2D and 3D) with different topologies. The evaluation results show that the selection of the ideal router is different depending on traffic patterns and design objectives. Overall, the mesh network with a four local ports router offers a higher level of performance with lower complexity compared to the traditional mesh with one local port router
Design and Implementation of Modified Partial Product Reduction Tree for High Speed Multiplication
Get PDFThis paper presents the details of hardware implementation of modified partial product reduction tree using 4:2 and 5:2 compressors. Speed of multiplication operation is improved by using higher compressors .In order to improve the speed of the multiplication process within the computational unit; there is a major bottleneck that is needed to be considered that is the partial products reduction network which is used in the multiplication block. For implementation of this stage require addition of large operands that involve long paths for carry propagation. The proposed architecture is based on binary tree constructed using modified 4:2 and 5:2 compressor circuits. Increasing the speed of operation is achieved by using higher modified compressors in critical path. Our objective of work is, to increase the speed of multiplication operation by minimizing the number of combinational gates using higher n:2 compressors. The experimental test of the proposed modified compressor is done using Spartan-3FPGA device (XC3S400 PQ-208). Using tree architectures for the partial products reduction network represent an attractive solution that is frequently applied to speed up the multiplication process. The simulation result shows 4:2 and 5:2 compressor output which is done using Questa Sim 6.4c Mentor Graphics tool
Implementation of Video Capture and Playback in Mobile Systems
Get PDFMobile phones are backbone of the mobile communications and have experienced fastest growing segment in the consumer market. In the 3G and 4G mobiles, video recording is an essential entertainment features so the user can record and play the video within the mobile phone. In this paper, video capture and playback implementation had been carried out by integrating the camera module to the GSM phone. An alaysis of the video processing had been carried out. Image sensor and LCD module had been interfaced with the base band processor through the video processor. To interface the different module necessary PCB schematic diagram had been arrived. Software implementation had been carried out for the Human Machine Interface for various settings of the camera module, which is integrated with the video processor. The developed playback system had been tested for the various senerious. In this video has been captured through the camera sensor and at the time of playback measured the resolution, power consumption and image transfer rates of the various modules used in the developed camera phone
Controller for Network Interface Card on FPGA
No full textThe continuing advances in the performance of network servers make it essential for network interface cards (NICs) to provide more sophisticated services and data processing. Modern network interfaces provide fixed functionality and are optimized for sending and receiving large packets. Network interface cards allow the operating system to send and receive packets through the main memory to the network. The operating system stores and retrieves data from the main memory and communicates with the NIC over the local interconnect, usually a peripheral component interconnect bus (PCI). Most NICs have a PCI hardware interface to the host server, use a device driver to communicate with the operating system and use local receive and transmit storage buffers. NICs typically have a direct memory access (DMA) engine to transfer data between host memory and the network interface memory. In addition, NICs include a medium access control (MAC) unit to implement the link level protocol for the underlying network such as Ethernet, and use a signal processing hardware to implement the physical (PHY) layer defined in the network. To execute and synchronize the above operations NICs also contents controller whose architecture is customized for network data transfer. In this paper we present the architecture of application specific controller that can be used in NICs