International Journal of Reconfigurable and Embedded Systems (IJRES)
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Simplified VHDL Coding of Modified Non-Restoring Square Root Calculator
Get PDFSquare root calculation is one of the most useful and vital operation in digital signal processing which in recent generations of processors, the operation is performed by the hardware. The hardware implementation of the square root operation can be achieved by different means, but it is very dependent on programmer's sense and ability to write efficient hardware designs. This paper offers universal and shortest VHDL coding of modified non-restoring square root calculator. The main principle of the method is similar with conventional non-restoring algorithm, but it only uses subtract operation and append 01, while add operation and append 11 is not used. The strategy has conducted to implement successfully in FPGA hardware, and offer an efficient in hardware resource, and it is superior
A Novel FPGA based Leading One Anticipation Algorithm for Floating Point Arithmetic Units
Get PDFIn multimedia Systems-on-Chips, the design of specialized IEEE-754-compliant floating point arithmetic units (FPU) is critical with respect to both operating speed and silicon area demand. Leading one anticipation is a well-known issue in the implementation of high speed FPUs. We investigated a novel leading one anticipation algorithm allowing us to significantly reduce the anticipation failure rate with respect to the state-of the art. We embedded our technique into a complete FPU and compared its performance against existing solutions, definitely showing both area savings and total latency reduction
Queued-Stack Dataflow Processing Element for a Cognitive Sensor Platform
Get PDFThis paper describes a Queued-Stack (QS) Dataflow Processing Element (DPE) that is used in a cognitive sensor platform. The queued-stack is used for buffering input data to the DPE and for storage of variables and results. The queuing mechanism and dataflow protocol provides the capability to compose multi-node computational systems where communication between elements is via non-blocking FIFO channels. System composition is achieved using synchronous dataflow tools such as SDF3 or Ptolemy. The dataflow-processing element is implemented using single cycle micro-coded engine where the ratio of datapath transistors to control logic is optimized for programmable energy-performance sensitive applications
Real-time Optical-flow Computation for Motion Estimation under Varying Illumination Conditions
Get PDFThe optical flow approach has emerged as a major technique for estimating object motion in image sequences. However, the obtained results by most optical flow techniques are poor because they are strongly affected by large illumination changes and by motion discontinuities. On the other hand, there have been two thrusts in the development of optical flow algorithms. One has emphasized higher accuracy; the other faster implementation. These two thrusts have been independently pursed, without addressing the accuracy vs. efficiency trade-offs. The optical flow computation requires high computing resources and is highly affected by changes in the illumination conditions in most of the existing techniques. In this paper, a new strategy for image sequence processing is proposed. The data reduction achieved with this strategy allows a faster optical flow computation. In addition, the proposed architecture is a hardware custom implementation in EP1S60F1020 FPGA showing the achieved performance