International Journal of Reconfigurable and Embedded Systems (IJRES)
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AES Encryption Algorithm Hardware Implementation: Throughput and Area Comparison of 128, 192 and 256-bits Key
Get PDFAdvanced Encryption Standard (AES) adopted by the National Institute of Standards and Technology (NIST) to replace existing Data Encryption Standard (DES), as the most widely used encryption algorithm in many security applications. Up to today, AES standard has key size variants of 128, 192, and 256-bit, where longer bit keys provide more secure ciphered text output. In the hardware perspective, bigger key size also means bigger area and small throughput. Some companies that employ ultra-high security in their systems may look for a key size bigger than 128-bit AES. In this paper, 128, 192 and 256-bit AES hardware are implemented and compared in terms of throughput and area. The target hardware used in this paper is Virtex XC5VLX50 FPGA from Xilinx. Total area and Throughput results are presented and graphically compared
Design and Development of Texture Filtering Architecture for GPU Application Using Reconfigurable Computing
Get PDFGraphical Processing Units (GPUs) have become an integral part of today’s mainstream computing systems. They are also being used as reprogrammable General Purpose GPUs (GP-GPUs) to perform complex scientific computations. Reconfigurability is an attractive approach to embedded systems allowing hardware level modification. Hence, there is a high demand for GPU designs based on reconfigurable hardware. The texture filter unit is designed to process geometric data like vertices and convert these into pixels on the screen. This process involves number of operations, like circle and cube generation, rotator, and scaling. The texture filter unit is designed with all necessary hardware to deal with all the different filtering operations. The designed texture filtering units are modelled in Verilog on Altera Quartus II and simulated using ModelSim tools. The functionality of the modelled blocks is verified using test inputs in the simulator.Circle and cube coordinates are generated for circle and cube generation. The work can form the basis for designing a complete reconfigurable GPU
FPGA Based a PWM Technique for Permanent Magnet AC Motor Drives
Get PDFThe permanent magnet AC motor trapezoidal (BLDC motor) is not strictly DC motor, which uses a pulsed DC fed to the stator field windings to create a rotating magnetic field. Therefore, the motor needs an electronic commutation to provide the rotating field. A pair of switches must be turned on sequentially in the correct order to energize a pair of windings. If the incorrect order is applied, then the BLDC motor will not operate properly. This paper presents a smart guideline to ensure that the order to energize a pair of windings is correct. To ensure the guideline, FPGA based a simple commutation state machine scheme to control BLDC motor is presented. The experiment results have shown that the guideline is correct. The commutation scheme was successfully realized using Altera's APEX20KE FPGA to control BLDC motor in both of forward/reverse rotations or forward/reverse regenerative braking properly
Effectual SVPWM Techniques and Implementation of FPGA Based Induction Motor Drive
Get PDFThis paper presents a field programmable gate array(FPGA)-based control integrated circuits(IC) for controlling the pulsewidth modulation (PWM) inverter used in power conditioning system for ac-voltage regulation. Space vector pulsewidth modulation(SVPWM) algorithm offers great flexibility to optimise switching waveform. Among them,double edge triggering can be implemented, It consumes less power compare to other PWM techniques. The SVPWM pulses thus generated through Xilinx is given as switching pulses to voltage source inverter(VSI) circuit to trigger the motor. The delay time of PWM output is programmable and SVPWM control IC is reprogrammable.It shows the advantage of lower total harmonic distortion(THD) without increasing the switching losses. Results are provided along with simulation analysis in terms of THD,output fundamental voltage and voltage transfer ratio to verify the feasibility of operation. The SVPWM switching pattern has been achieved with a fundamental frequency of 50HZ
VHDL Implementation of H.264 Video Coding Standard
Get PDFThis Paper contains VHDL implementation of H.264 video coding standard, which is new video coding standard of the ITU-T Video Coding Experts Group and the ISO/IEC Moving Picture Experts Group. The main goal of the H.264/AVC standardization effort is to enhance compression performance and provision of a “network-friendly” video representation addressing “conversational” (video telephony) and “no conversational” (storage, broadcast, or streaming) applications.H.264 video coder standard is having fundamental blocks like transform and quantization, Intra prediction, Inter prediction and Context Adaptive Variable Length Coding (CAVLC). Each block is designed and integrated to one top module in VHDL
FPGA Implementation of a 64-Bit RISC Processor Using VHDL
Get PDFIn this paper, the Field Programmable Gate Array (FPGA) based 64-bit RISC processor with built-in-self test (BIST) feature implemented using VHDL and was, in turn, verified on Xilinx ISE simulator. The VHDL code supports FPGA, System-On-Chip (SOC), and Spartan 3E kit. This paper also presents the architecture, data path and instruction set (IS) of the RISC processor. The 64-bit processors, on the other hand, can address enormous amounts of memory up to 16 Exabyte’s. The proposed design can find its applications in high configured robotic work-stations such as, portable pong gaming kits, smart phones, ATMs
Vehicle Accident Automatic Detection and Remote Alarm Device
Get PDFThe Rapid growth of technology and infrastructure has made our lives more easy . The advent of technology has also increased the traffic hazards and the road accident take place frequently which causes huge loss of life and property because of the poor emergency facilities. Our project will provide an optimum solution to this draw back. An accelerometer can be used in a car alarm application so that dangerous driving can be detected . It can be used as a crash or rollover detector of the vehicle during and after a crash. With signals from an accelerometer, a severe accident can be recognized. According to this project when a vehicle meets with an accident immediately Vibration sensor will detect the signal or if a car rolls over, an Micro electro mechanical system(MEMS) sensor will detects the signal and sends it to ARM controller. Microcontroller sends the alert message through the GSM MODEM including the location to police control room or a rescue team. So the police can immediately trace the location through the GPS MODEM, after receiving the information. Then after conforming the location necessary action will be taken. If the person meets with a small accident or if there is no serious threat to anyone`s life, then the alert message can be terminated by the driver by a switch provided in order to avoid wasting the valuable time of the medical rescue team. This paper is useful in detecting the accident precisely by means of both vibration sensor and Micro electro Mechanical system(MEMS) or accelerometer. As there is a scope for improvement and as a future implementation we can add a wireless webcam for capturing the images which will help in providing driver`s assistance. Keywords - Accident ,Automatic Detection, Micro electro Mechanical system , Remote Alarm Device, Vehicl
Digital Control of Static Var Compensator with Field Programmable Gate Array
Get PDFThis paper is about real time simulation and implementation of FPGA Digital Control of Static VAR compensator for 750km lab model of artificial transmission line. In this paper, a new method of controlling SVC using Field Programmable Gate Array (FPGA) is suggested. FPGA controller is used to generate the firing pulses required to for Static Var Compensator. Pulses are synchronized with AC input; the delay of pulses determines the firing angle to driver circuit. The proposed control scheme has been realized using XILINX FPGA SPARTAN 2 XC2S200 and tested actual testing proves that these devices when installed, they keep the bus voltage same as reference voltage (sending-end voltage). The results are prominent and give a way for real-time implementation of the proposed control schemes. These control schemes are simulated for the real-time control along with real-time modeling and simulations.The results are prominent and give a way for real-time implementatio
Attendance Logging In Webserver Using Multi Node Embedded System Connected Through Wi-Fi
No full textIn the present age, we are in need of fully automated attendance logging system. The design of Remote Attendance Logging System and its control is a challenging part. RFID reader reads the RFID tag, and the details of the tag is logged in the embedded system. The Web based distributed measurement and control is slowly replacing parallel architectures due to its non-crate architecture which reduces complexities. A new kind of expandable, distributed large attendance logging system based on ARM Cortex M3 boards has been investigated and developed in this paper, whose hardware boards use 32-bit RISC processor with wifi dongle attached to its USB port, and software platform use Keil MDK-ARM for firmware and HTML for man machine interface. This system can display date and time of log in and log out of a person. The data can be displayed on web pages at different geographical locations, and at the same time can be transmitted to a Remote Data Acquisition System by using HTTP protocol. The embedded board can act as a central CPU to communicate between web servers automatically
A Novel High Speed FPGA Architecture for FIR Filter Design
Get PDFThis paper presents the details of hardware implementation of linear phase FIR filter using merged MAC architecture. Speed of convolution operation of FIR filter is improved using merged MAC architecture. By exploiting the reduced complexity made possible by the use of sparse powers of two partial products terms coefficients, an FIR filter tap can be implemented with 2B full adders, and 2B latches, where B is intermediate wordlegnth. Word and bit level parallelism allows high sampling rates, limited only by the full adder delay. The proposed architecture is based on binary tree constructed using modified 4:2 and 5:2 compressor circuits. Increasing the speed of operation is achieved by using higher modified compressors in critical path. Our objective of work is, to increase the speed of multiplication and accumulation operation by minimizing the number of combinational gates using higher n: 2 compressors, which is required more for Array multiplier at the time of implementation of array architecture. This novel architecture allows the implementation of high sampling rate filters of significant length on FPGA Spartan-3 device (XC3S400 PQ-208). The simulation result shows convolution output of digital FIR filter which is done using Questa Sim 6.4c Mentor Graphics tool. The experimental test of the proposed digital FIR filter is done using Spartan-3 device (XC3S400 PQ-208