International Journal of Reconfigurable and Embedded Systems (IJRES)
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Design of AES Algorithm for 128/192/256 Key Length in FPGA
Get PDFThe cryptographic algorithms can be implemented with software or built with pure hardware. However Field Programmable Gate Arrays (FPGA) implementation offers quicker solution and can be easily upgraded to incorporate any protocol changes. The available AES algorithm is used for data and it is also suitable for image encryption and decryption to protect the confidential image from an unauthorized access. This project proposes a method in which the image data is an input to AES algorithm, to obtain the encrypted image. and the encrypted image is the input to AES Decryption to get the original image. This project proposed to implement the 128,192 & 256 bit AES algorithm for data encryption and decryption, also to compare the speed of operation, efficiency, security and frequency . The proposed work will be synthesized and simulated on FPGA family of Xilink ISE 13.2 and Modelsim tool respectively in Very high speed integrated circuit Hardware Description Language (VHDL)
Bilinear Interpolation Image Scaling Processor for VLSI Architecure
Get PDFWe introduce image scaling processor using VLSI technique. It consist of Bilinear interpolation, clamp filter and a sharpening spatial filter. Bilinear interpolation algorithm is popular due to its computational efficiency and image quality. But resultant image consist of blurring edges and aliasing artifacts after scaling. To reduce the blurring and aliasing artifacts sharpening spatial filter and clamp filters are used as pre-filter. These filters are realized by using T-model and inversed T-model convolution kernels. To reduce the memory buffer and computing resources for proposed image processor design two T-model or inversed T-model filters are combined into combined filter which requires only one line buffer memory. Also, to reduce hardware cost Reconfigurable calculation unit (RCU)is invented. The VLSI architecture in this work can achieve 280 MHz with 6.08-K gate counts, and its core area is 30 378 μm2 synthesized by a 0.13-μm CMOS process
FPGA based Multichannel Bit Error Rate Tester for Spacecraft Data Acquisition System
Get PDFBit Error Rate (BER) is a principle measure of data transmission link performance. BER tester (BERT) consists of a Pattern Generator and an Analyzer that can be set to the same pattern. The payload data transmitted from the spacecraft consists of one, two or three channels per carrier based on the modulation scheme. The traditional equipments can do BER analysis for only one channel at a time. In order to support multichannel BER analysis, a Personal Computer (PC) based system is designed and implemented in Altera Stratix II (EP2S130F1508C5N) FPGA. Ethernet is configured using WIZnet 5300 (Ethernet Controller) and it is used for communication between FPGA and PC with an application. Application is used to transmit the Pattern Generator’s configurations from PC to FPGA and to receive Analyzer’s status. Packet processing is done for this communication using User Datagram protocol (UDP). On the whole, traditional equipments are replaced by the designed and implemented bit error rate tester
FPGA Evaluation of Reconfigurable Modules With Fault Detection and Repair Technique
Get PDFThis paper proposes a fault detection and repair algorithm which is suitable for fault free reconfigurable systems. In recent years Built in Self Repair digital systems have got very important role in the applications such as nuclear systems, space missions and communication systems etc where system reliability is very critical . Systems designed to operate in critical conditions will collapse due to even a single fault occurrence. To avoid these situations many methods have developed in recent years. This work proposes an area efficient and fast fault detection and repair algorithm. For the evaluation of the new approach and older methods a system with a standalone module and four add on modules were designed and evaluated for resource utilization using XUPV5 board. The entire FPGA is divided in to tiles and each module is implemented in different tiles using partial reconfiguration method using Xilinx Plan Ahead 14.2 with partial reconfiguration facility
Crosstalk Minimization in VLSI Interconnects
Get PDFCrosstalk noise is often induced in long interconnects running parallel to each other .There arises a need to minimize the effect of these crosstalk noise so as to maintain the signal integrity in interconnects. So in this paper crosstalk noise is minimized using various techniques such as repeater (bidirectional buffer) insertion along with shielding, skewing and shielding & skewing simultaneously. With the help of these techniques crosstalk noise is controlled to a great extent in long interconnects. Prelayout simulations for crosstalk are carried out for different techniques at 90nm technology nodes using cadence. The influences of these techniques are analyzed and it is found that crosstalk is reduced upto 57%
Low Power VLSI Design and Implementation of Area-Optimized 256-bit AEStandard for Real Time Images on Vertex 5
Get PDFA new Vertex6-chipscope based implementation scheme of the AES-256 (Advanced Encryption Standard, with 256-bit key) encryption and decryption algorithm is proposed in this paper. For maintaining the speed of encryption and decryption, the pipelining technology is applied and the mode of data transmission is modified in this design so that the chip size can be reduced. The 256-bit plaintext and the 256- bit initial key, as well as the 256-bit output of cipher-text, are all divided into four 32-bit consecutive units respectively controlled by the clock. In this novel work, substantial improvement in performance in terms of area, power and dynamic speed has been obtained
Embedded Linux Based Shopping Assistance System
Get PDFIn a view to streamline shopping system and facilitate access to required commodities among innumerable varieties in a super market, personalized service can be exploited in automated manner through interactive graphical user interface. Implementation of location based several touch screen modules with a centralized database can provide easy, accurate and timely information in regards to query generated by the users. Availability of an item and its location with absolute identification are displayed on the screen to facilitate users to get access to it immediately. This not only saves valuable time and cumbersome manual procedure in finding desired products but also provides an easy-to-use interactive shopping experience without any effort. Personalized Shopping Assistance maintains a centralized database for all products in the super market with user-friendly graphical user interface touch screen modules at various locations
A Novel Evolutionary Method for Designing Optimized Multifunctional Logic Modules
Get PDFIn this paper, we proposed a novel heuristic method based on Imperialist competitive Algorithm (ICA) to design combinational logic modules which performing different arithmetic functions. According to conventional methods, for multi functional circuit, a distinct circuit is designed for each specific function and then all of them are combined together with multiplexer(s) to have desired circuit. But in our proposed method the whole circuit structure is designed and optimized in one procedure by ICA Algorithm. We tried to optimize the area of circuit by reducing the number of transistors forming logic gates. Simulation results show that our method significantly reduces the number of transistors and gates and accordingly the circuit area
CO Pollution Warning System for Indoor Parking Area Using FPGA
Get PDFFrom some compounds used as parameters in air pollution-such as O3, Particulate Materials, CO, NO2, SO2 and Pb-CO is the most common cause of poisoning accidents. Indoor parking area is one sample of potential area for CO pollution. However, according to the scientific nature of CO-tasteless, colorless, and odorless-people exposed to CO are usually not aware that s/he exposed to dangerous levels of CO. This research aimed to make a prototype of an embedded system that can monitor air pollution, give an effective warning and it should be affordable. The prototype of CO air pollution alert system has been successfully built using FPGA Xilinx Spartan 3E as the major component. Sensor Hanwei MQ7 used in this prototype has been tested in a simulation box using cigarette smoke as CO pollutant and the reading result has met the characteristic curve in the datasheet. The system interface has met user satisfaction with MOS value 4.31 from 5 scales. Based on the response time testing, we conclude that FPGA is suitable to be used in a system that performs fast parallel processing based on logical actions from the input given
Optimization and Implementation of Reversible BCD Adder in Terms of Number of Lines
Get PDFThe Reversible logic plays an important role to obtain the minimal energy dissipation. It is the main requirement in the low power digital design. To implement a reversible function some additional lines are required. Sometimes it is more than the primary inputs which leads to increased size of the circuit. Hence the reducing the number of circuit lines is one of the major criterion in reversible logic. The general idea is to merge the garbage output lines with appropriate constant input lines. In this work, Toffoli gate implementation of BCD adder and press gate implementation of BCD adder is taken and an optimization algorithm has been applied to reduce the number of lines in the circuit. The kit used to implement the design is Vertex5 in which both the area and delay are analyzed