International Journal of Reconfigurable and Embedded Systems (IJRES)
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Design and Development of ARM9 Evaluation Kit for Embedded Applications
Get PDFIn contrast with low end microprocessor, ARM9 core is quite a sophisticated processor. The Evaluation kit plays an important role in the prototype development and verification of the system design before taking to its actual system development hence it’s provide better confidence to the designer. In this paper a project for the Evaluation kit has been designed for embedded system engineer to implement and confirm the functionality of their operating systems which could lead to a comfortable deployment. The independent modules for the interfaces of the ARM9 processor have been designed and the schematics have been developed using OrCAD. From the tested schematics designed in OrCAD, the related PCB is designed using CADSTAR. An eight-layer board is designed for its signal integrity and complexity of the schematic designed. The designed PCB layer is then calibrated and Gerber files are then made and passed on the PCB board manufacturer for PCB fabrication. The PCB board made is then tested for interconnection continuity using multi-meter as the components are loaded on to the board
Design and Implementation of an Ethernet MAC IP Core for Embedded Applications
Get PDFAn IP (intellectual property) core is a block of logic or data that is used in making a field programmable gate array (FPGA) or application-specific integrated circuit (ASIC) for a product. As essential elements of design reuse, IP cores are part of the growing electronic design automation (EDA) industry trend towards repeated use of previously designed components. Ethernet continues to be one of the most popular LAN technologies. Due to the robustness resulting from its wide acceptance and deployment, there has been an attempt to build Ethernet-based real-time control networks for manufacturing automation. There is a growing demand for low cost, power efficient MAC IP Core for various embedded applications. In this paper a project is discussed to design an Ethernet MAC IP Core solution for such embedded applications. The proposed 10_100_1000 Mbps tri-mode Ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed to use less than 2000 LCs/LEs to implement full function. It will use inferred RAMs and PADs to reduce technology dependence. To increase the flexibility, three optional modules can be added to or removed from the project. A GUI configuration interface, created by Tcl/tk script language, is convenient for configuring optional modules, FIFO depth and verification parameters. Furthermore, a verification system was designed with Tcl/tk user interface, by which the stimulus can be generated automatically and the output packets can be verified with CRC-32 checksum. A solution which would consume a smaller part of the targeted FPGA, and thus giving room for other on-chip peripherals or enable the use of a smaller sized FPGA. To employ a smaller FPGA is desirable since it would reduce power consumption and device price
Decision Based Median Filter algorithm using Resource Optimized FPGA to Extract Impulse Noise
Get PDFMedian filter is a non-linear filter used in image processing for impulse noise removal. It finds its typical application in the situations where edges are to be preserved for higher level operations like segmentation, object recognition etc. This paper presents an accurate and efficient noise detection and filtering algorithm for impulse noise removal. The algorithm includes two stages: noise detection followed by noise filtering. The proposed algorithm replaces the noisy pixel by using median value when other pixel values, 0’s or 255’s are present in the selected window and when all the pixel values are 0’s and 255’s then the noise pixel is replaced by mean value of all the elements present in the selected window. Similarly algorithm checks for five different conditions to preserve image details, object boundary in high level of noise densities. This median filter was designed, simulated and synthesized on the Xilinx family of FPGAs (XC3S500E of Spartan-3E). The VHDL was used to design the above 2-D median filter using ISE (Xilinx) tool & tested & compared for different grayscale images
Design and Implementation of Adaptive FIR filter using Systolic Architecture
Get PDFThe tremendous growth of computer and Internet technology wants a data to be process with a high speed and in a powerful manner. In such complex environment, the conventional methods of performing multiplications are not suitable to obtain the perfect solution. To obtain perfect solution parallel computing is use in contradiction. The DLMS adaptive algorithm minimizes approximately the mean square error by recursively altering the weight vector at each sampling instance. In order to obtain minimum mean square error and updated value of weight vector effectively, systolic architecture is used. Systolic architecture is an arrangement of processor where data flows synchronously across array element. This project demonstrates an effective design for adaptive filter using Systolic architecture for DLMS algorithm, synthesized and simulated on Xilinx ISE Project navigator tool in very high speed integrated circuit hardware description language (VHDL) and Field Programmable Gate Arrays (FPGAs). Here, by combining the concept of pipelining and parallel processing in to the systolic architecture the computing speed increases
Design of AES Pipelined Architecture for Image Encryption/Decryption Module
Get PDFThe relentless growth of Internet and communication technologies has made the extensive use of images unavoidable. The specific characteristics of image like high transmission rate with limited bandwidth, redundancy, bulk capacity and correlation among pixels makes standard algorithms not suitable for image encryption. In order to overcome these limitations for real time applications, design of new algorithms that require less computational power while preserving a sufficient level of security has always been a subject of interest. Here Advanced Encryption Standard (AES),as the most widely used encryption algorithm in many security applications. AES standard has different key size variants, where longer bit keys provide more secure ciphered text output. The available AES algorithm is used for data and it is also suitable for image encryption and decryption to protect the confidential image from an unauthorized access. This project proposes a method in which the image data is an input to Pipelined AES algorithm through Textio, to obtain the encrypted image. and the encrypted image is the input to Pipelined AES Decryption to get the original image. This project proposed to implement the 128,192 & 256 bit Pipelined AES algorithm for image encryption and decryption, also to compare the latency , efficiency, security, frequency & throughput . The proposed work will be synthesized and simulated on FPGA family of Xilink ISE 13.2 and Modelsim tool respectively in Very high speed integrated circuit Hardware Description Language
FPGA Based Firewall using Embedded Processor for Vulnarability Packet Detection
Get PDFThis paper describes the design of high performance packet filtering firewall using embedded system. An FPGA (field programmable gate array) platform has been used for implementation and analysing the network firewall. It is capable of accepting real time changes. This network security application has an ability to perform powerful protection against unwanted data packets such as virus attack, spam in e-mails, hackers, worms, spyware unauthorized contents. However the firewalls don’t address the difficulty of unwanted data packets intrusion. The ultimate aim of this work is to create a systematic way of approach for unwanted packets discard in a network system. We use a specially trained algorithms such as Wu-manber algorithms (high performance, multi-pattern matching), bloom filter algorithm (space efficient data structure for testing an element in the set.Our design is mainly based on machine learning and artificial intelligence. This gives a high efficiency, improved performance and high ability of packet detection with less contribution of time in an effective way
Implementation of LOCO-I Lossless Image Compression Algorithm for Deep Space Applications
Get PDFPresent emerging trend in space science applications is to explore and utilize the deep space. Image coding in deep space communications play vital role in deep space missions. Lossless image compression has been recommended for space science exploration missions to retain the quality of image. On-board memory and bandwidth requirement is reduced by image compression. Programmable logic like field programmable gate array (FPGA) offers an attractive solution for performance and flexibility required by real time image compression algorithms. The powerful feature of FPGA is parallel processing which allows the data to process quicker than microprocessor implementation. This paper elaborates on implementing low complexity lossless image compression algorithm coder on FPGA with minimum utilization of onboard resources for deep space applications
Implementation of High Speed Self Switching Frequency Agile RADAR
Get PDFThe radar has to resist diversified jamming; High Speed self-adaptive frequency agility is an important and effective function for radars to resist jamming. The procedure to achieve this function are described, and the function is realized with FPGA using Hardware description Language, the validity is proved by on- line sampling and simulation. The High speed self-adaptive frequency agility module can analyze the type of jamming to select transmitting frequency to avoid the frequencies which have interference, under frequency diversity and fixed frequency, respectively. The general application on a searching radar shows that the module has good real-time and anti- jamming capacity
Realization of Programmable BPSK Demodulator-Bit Synchronizer using Multirate Processing
Get PDFThis paper presents the design and implementation of programmable BPSK demodulator and bit synchronizer. The demodulator is based on the Costas loop design whereas the bit synchronizer is based on Gardner timing error detector. The advantage of this design is that it offers programmability using multi-rate processing and does not rely on computation of filter coefficients, NCO angle input for each specific data rate and thus avoids computational complexities. The algorithm and its application were verified on Matlab-Simulink and were implemented on ALTERA platform. A 32 kHz BPSK demodulator–bit synchronizer pair catering for a data rate from 1kbps to 8kbps was implemented
Development of Wireless Sensor Network for Traffic Monitoring Systems
Get PDFTraffic congestion has been a major problem on roads around the world. In addition, there is increase in volume of traffic vehicle density at a steady rate. Thus traffic on major roads has to be controlled to keep the traffic flowing at an acceptable rate. Several schemes for replacing the predominantly used Round Robin (RR) scheme for reducing congestion at traffic junctions have been proposed. Dynamic traffic control schemes adapt to the changing traffic by monitoring the state (such as the number queued up on each lane.). These need appropriate sensing and monitoring systems. In this paper a traffic monitoring and control system based on AMR (Anistropic Magneto Resistive) vehicle sensors, wireless sensor network and a proiritised Weighted Round Robin (WRR) scheduling technique, is developed.AMR sensors installed in road pavement detect the number of vehicles waiting in a traffic lane. The AMR sensors are connected to the master controller to form a Zigbee based sensor network. The master node consists of an ARM processor integrated with a Zigbee masternode. The traffic control algorithm is implemented at master node which is responsible for taking traffic signaling decision. It receives sensor data from all the lanes. A two level priority algorithm with weighted round robin scheduling, where first and second maximum weighted lane are to pass the signal is developed, To avoid starving the least loaded lanes, a cycle of normal round robin scheduling is performed after four rounds of proiritised weighted round robin schedule. The proposed algorithm is simulated and compared with the standard round robin algorithm. The developed algorithm decreases the average waiting time for a commuter while maintaining the average throughput up to average loads. The development traffic monitoring system is successfully demonstrated for a four lane junction