International Journal of Reconfigurable and Embedded Systems (IJRES)
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Development of BSP for ARM9 Evaluation Board
Get PDFWith an increasing usage of ARM9 core for different kinds of applications ranging from data acquisition to Mobile application, there arises the need for developing ARM9 based board. To bring up this board, board supporting package (BSP) is must. Board supporting package virtualizes the platform hardware so that the different drivers can be ported easily on any hardware. The boot loader is the initial stage of firmware, which initializes the hardware components presents on the board. A universal Bootloader is chosen and is to be customized with respect to target board. In the later section bootloader is interfaced to the kernel which is obtained form an authorized distributor under general purpose license. The customized board specific routines as well drivers are ported onto the hardware. Then the compiled kernel image is ported onto the target board using a debugger and SAM-BA utility. Linux kernel has seen major releases; the basic architecture of the Linux kernel has remained more or less unchanged. The latest 2.6 version of Linux kernel is ported onto target hardware. Kernel support for many architectures and high-end I/O devices gives the independence to choose appropriate hardware for developing system. The bootloader customization is the critical step, which involves a lot of modifications in the header files. BSP components such as bootloader, kernel is compiled using GNU tool chain; obtained image is ported on target using debugger. BSP porting is a very complex task, which required knowledge of hardware and software control sequence and boot strategy of the controller
Implementation of PI Controller for 3ф BLDCM Drive Using FPGA
Get PDFDespite the need of a complex motor controller, the simple construction of BLDC motors offers several inherent advantages not provided with brushed DC motors in terms of low inertia, high torque and a very wide speed range. The BLDC motors include, Longer service life due to a lack of electrical and friction losses and also free maintenance due to a lack of brushes and mechanical commutators. The EMI and noise are reduced because of the elimination of ionizing spikes from brushes. The control system of BLDCM is highly complex drive due to nonlinear nature. In such a system for implementing control algorithm needs high speed processor. In this work the controller Xilinx Spartan-6 FPGA is a demonstration platform intended to become familiar with the new features and availability of the Spartan-6 FPGA. The various experimental tests are carried out in 3Ф BLDCM .The experimental results are reported in order to verify the steady state, transient and robustness performance of the controller
An Efficient VLSI Architecture for Nonbinary LDPC Decoder with Adaptive Message Control
Get PDFA new decoder architecture for nonbinary low-density parity check (LDPC) codes is presented in this paper to reduce the hardware operational complexity and power consumption. Adaptive message control (AMC) is to achieve the low decoding complexity, that dynamically trims the message length of belief information to reduce the amount of memory accesses and arithmetic operations. A new horizontal nonbinary LDPC decoder architecture is developed to implement AMC. Key components in the architecture have been designed with the consideration of variable message lengths to leverage the benefit of the proposed AMC. Simulation results demonstrate that the proposed nonbinary LDPC decoder architecture can significantly reduce hardware operations and power consumption as compared with existing work with negligible performance degradation
Design of Secure Transmission of Multimedia Data Using SRTP on Linux Platform
Get PDFThis paper aims for providing a viable solution for security in streaming media technology. Service providers do not want the end users to capture and duplicate streaming media data. Once captured data can be re-distributed to millions without any control from the source. Licensing issues also dictate the number of times end user may utilize the data. Encryption is not sufficient as it leaves the system vulnerable to duplication and recording after decryption. In this paper an attempt has been made to transmit digital multimedia data to multiple users. The transmission of the video/audio data has been attempted from one PC to another PC. While doing this, security considerations have to be taken care by using suitable encryption/decryption techniques. A research carried out on the different data transmission protocols reveals that the Secure Real Time Transport Protocol (SRTP) is one of the best available protocols. Hence the SRTP has been deployed in this project on Linux OS using socket programming. The code for the transmitter and the receiver is designed and developed around the SRTP library for transmission of multimedia data. The solution is illustrated by choosing an example of a video clip for transmission and reception. This model increasing the security of streaming media and adds a measure of integrity protection, but it is primarily intended to aid in replay preventions
An Efficient approach for Design and Testing of FPGA Programming using LabVIEW
Get PDFProgramming of Field Programmable Gate Arrays (FPGAs) have long been the domain of engineers with VHDL or Verilog expertise.FPGA’s have caught the attention of algorithm developers and communication researchers, who want to use FPGAs to instantiate systems or implement DSP algorithms. These efforts however, are often stifled by the complexities of programming FPGAs. RTL programming in either VHDL or Verilog is generally not a high level of abstraction needed to represent the world of signal flow graphs and complex signal processing algorithms. This paper describes the FPGA Programs using Graphical Language rather than Verilog, VHDL with the help of LabVIEW and features of the LabVIEW FPGA environment
Software Design and Development of Beverage Vending Machine System Using ARM Architecture with LPC2148
Get PDFBeverage vending machine systems are becoming popular in the Indian market.These systems are today available in Indian MNCs and some top rated restaurants and hotels.In most systems the operation are carried manually by the operator in which the billing and change making is carried out by the owner who runnig the shop or restaurant.In India tea and coffee habits were cultured by the colonial rule of the British and the Portuguese,even tody the colonial rule had been over but the habits of tea and coffee beverage consumptions becomes as the routine daily life.Hence there is a need to understand beverage vending machine systems to serve the Indian Market. In this paper,a critical analysis of requirement has been carried out and the system design had been arrived at.The system requirement demand an ARM based controller for better system performance.To meet the system performance criteria and richest of peripherals an LPC2148 with low cost had been selected.The system is more efficient to analyse the change making and the identification had been carried out using the motors,LCDs,water heater,solenoid valve,money box,change making and dispensing unit. The system is tested and validated for the specified test cases.The milk motor run for 10 rotations to drive 200 milligrams of milk powder to the container to make to tea or coffee beverage.In this system a stepper motor had been used can be replaced by using dc motors to avaoid power losses.In future an ATM or credit card based payment system can be incorporated to these systems
A New-High Speed-Low Power-Carry Select Adder Using Modified GDI Technique
Get PDFAdders are of fundamental importance in a wide variety of digital systems. This paper presents a novel bit block structure which computes propagate signals as carry strength. Power consumption is one of the most significant parameters of carry select adder.The proposed method aims on GDI(Gate Diffusion Input) Technique. Modified GDI is a novel technique for low power digital circuits design further to reduce the swing degradation problem. This techniques allows reduction in power consumption, carry propagation delay and transistor count of the carry select adder.This technique can be used to reduce the number of transistors compared to conventional CSLA and made comparison with known conventional adders which gives that the usage of carry-strength signals allows high-speed adders to be realised at lower cost as well as consuming lower power than previous designs. Hence, this paper we are concentrating on the area level &we are reducing the power using modified GDI logic
Dynamic Partial Reconfiguration with FIR Filter Application
Get PDFDynamic partial reconfiguration has evolved as a very prominent state of art for efficient area utilization of Field Programmable Gate Array (FPGA) as well as significant reduction in its overall power consumption when properly used to lessen the idle logic on FPGA. It provides desired results even as the computational complexity increases in the field of Digital Signal Processing. This paper explains Dynamic Partial Reconfiguration (DPR) with an example of Finite Impulse response (FIR) filter of order 10. Initially RTL coding for Direct Form FIR structure is written in Verilog in fixed point format for low pass and high pass filter modules using ISE Design suite. Functioning of the both the modules is verified individually through hardware co-simulation on ZYBO (Zynq Board) from Digilent using Black Box from System Generator. Finally dynamic partial reconfigurable FIR filter with low pass and high pass as reconfigurable modules is implemented on ZYBO using PlanAhead tool. Final comparison of resource utilization with and without DPR is presente
FPGA Synthesis of Reconfigurable Modules for FIR Filter
Get PDFReconfigurable computing for DSP remains an active area to explore as the need for incorporation with more conventional DSP technologies turn out to be obvious. Conventionally, the majority of the work in the area of reconfigurable computing is aimed on fine grained FPGA devices. Over the years, the focus is shifted from bit level granularity to a coarse grained composition. FIR filter remains and persist to be an important building block in various DSP systems. It computes the output by multiplying input samples with a set of coefficients followed by addition. Here multipliers and adders are modeled using the concept of divide and conquer. For developing a reconfiguarble FIR filter, different tap filters are designed as separate reconfigurable modules. Furthermore, there is an additional concern for making the system fault tolerant. A fault detection mechanism is introduced to detect the faults based on the nature of operands. The reconfigurable modules are structurally modeled in Verilog HDL and simulated and synthesized using Xilinx ISE 14.2. A comparison of the device utilization of reconfigurable modules is also presented in this paper by implementing the design on various Virtex FPGA devices
Wireless Sensor Network for Performance Monitoring of Electrical Machine
Get PDFThis paper proposes a novel industrial wireless sensor network for industrial machine condition monitoring. To avoid unexpected equipment failures and obtain higher accuracy in diagnostic and prognostic for the health condition of a motor, efficient and comprehensive data collecting, monitoring, and control play an important role to improve the system more reliable and effective. A novel wireless data collection for health monitoring system of electric machine based on wireless sensor network is proposed and developed in this paper. The unique characteristics of ZigBee networks such as low power, low cost, and high flexibility make them ideal for this application. The proposed system consists of wireless sensor nodes which are organized into a monitoring network by ZigBee protocols. A base station and wireless nodes have been developed to form a prototype system. Various sensors have the capability to monitor physiological as well as environmental conditions. Therefore proposed system provides a flexible solution that makes our living spaces more intelligent