International Journal of Reconfigurable and Embedded Systems (IJRES)
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Design and Implementation of Recursive Least Square Adaptive Filter Using Block DCD approach
Get PDFDue to the explosive growth of multimedia application and tremendous demands in Very Large Scale Integrated (VLSI), there is a need of high speed and low power digital filters for digital signal processing applications. In Digital Signal Processing (DSP) systems, Finite Impulse Response (FIR) filters are one of the most common components which is used, by convolving the input data samples with the desired unit sample response of the filter. The proposed work deals with the design and implementation of RLS adaptive filter using block DCD approach. The evaluation of speed, area and power for proposed work will be done. Also, the comparison of the proposed design with the existing will be carried out for various input combinations
An Integrated Architectural Clock Implemented Memory Design for Embedded System
No full textRecently Low power custom memory design is the major issue for embedded designer. Micro wind and Xilinx simulator performs efficient cache simulation and high performances with low power consumption. SRAM efficiency analyzed with 6-T architecture design and analyzed the simulation performance for specific application. We have implemented clock based memory architecture design and analyzed internal clock efficiency for SRAM. Architectural clock implemented memory design that reduces access time and propagation delay time for embedded devices. Internal semiconductor material improvement increases simulation performance and these design implemented for application specific design architecture
Application of New Approach of design flow for Hardware/Software Embedded System with the Use of Design Patterns in Fuzzy control system
Get PDFThis paper present a new method of conception of hardware/software embedded system design methodology based on use of design pattern approach called Abstract_factory. We called this new design tool “smart cell”. The main idea of the conception of embedded systems design is based on the used of object-oriented design ULM2.0. When the smart-cell is implemented, we justify their uses as a design tool that allows, first, to develop a specified application of fuzzy controller called PDC (parallel distributed conpensation). Second, the specification of the generation phases of the system architecture design, and eventually partitioning the application on heterogeneous platform based on hardware resource DSP and FPGA software to illustrate the proposed approach
FPGA Based Controller Area Network
Get PDFIn this paper the Controller Area Network (CAN) Controller is presented. CAN is an advance serial bus communication protocol that efficiently supports distributed, broadcast real-time control and fault tolerance features for automobile industries to provide congestion free networking. The CAN Controller is designed for scheduling of messages, consist of the Transmitter Controller, FIFO buffer, CRC generator and bit stuffer. Scheduling messages on CAN corresponds to assigning identifiers (IDs) to message according to their priorities. Non Return to Zero (NRZ) coding and Non Destructive Bitwise Arbitration (NDBA) is used. The data is taken from the buffer FIFO, bit stuffed and then transmitted after CRC is performed. The whole design is captured entirely in VHDL language using bottom up design and verification methodology. The proposed controller was designed for applications needing high level data integrity and data rates upto 1Mbps. The applications of CAN are factory automation, machine control, automobile, avionics and aerospace, building automation
An Efficient Framework for Floor-plan Prediction of Dynamic Runtime Reconfigurable Systems
Get PDFSeveral embedded application domains for reconfigurable systems tend to combine frequent changes with high performance demands of their workloads such as image processing, wearable computing andnetwork processors. Time multiplexing of reconfigurable hardware resources raises a number of new issues, ranging from run-time systems to complex programming models that usually form a Reconfigurablehardware Operating System (ROS). The Operating System performs online task scheduling and handles resource management.There are many challenges in adaptive computing and dynamic reconfigurable systems. One of the major understudied challengesis estimating the required resources in terms of soft cores, Programmable Reconfigurable Regions (PRRs), the appropriate communication infrastructure, and to predict a near optimal layout and floor-plan of the reconfigurable logic fabric. Some of these issues are specific to the application being designed, while others are more general and relate to the underlying run-time environment.Static resource allocation for Run-Time Reconfiguration (RTR) often leads to inferior and unacceptable results. In this paper, we present a novel adaptive and dynamic methodology, based on a Machine Learning approach, for predicting andestimating the necessary resources for an application based on past historical information.An important feature of the proposed methodology is that the system is able to learn and generalize and, therefore, is expected to improve its accuracy over time. The goal of the entire process is to extract useful hidden knowledge from the data. This knowledge is the prediction and estimation of the necessary resources for an unknown or not previously seen application
Design of Low Power Dual Dynamic Node Flip-Flop Using Sleep Transistor with NMOS
Get PDFThis paper introduces a Low Power Dual DynamicNode FlipFlop(DDFF) using Sleep Transistor with NMOS. Theproposed design retains the logic level till the end of evaluation and pre-charge mode. The low power DDFF architecturethat combines the advantages of dynamic and static CMOSstructures. The Sleep Transistors approach are used for leakagepower reduction. It reduces leakage current in ideal mode.The performance of the proposed flip flop was compared withthe conventional dual dynamic node flip flop (DDFF) in 90nmCMOS technology with 1.2v supply voltage at room temperatures.Also, conventional DDFF and DDFF using Sleep Transistor withNMOS are compared with other complicated designs and realizesby a 4-bit Johnson up and down counter. The performanceimprovements indicates that the proposed designs are suited formodern high-performance CMOS circuits where leakage powerand power delay product overhead are of major concer
Design and Implementation of Four Bit Binary Shifter Circuit Using Reversible Logic Approach
Get PDFShifter circuits are the key component of arithmetic logic unit as well as storage unit of any digital computing device. Designing these shifter circuits using reversible logic approach leads to create low power loss digital systems. Reversible circuit design approach is nowadays widely applicable in various disciplines such as Nanotechnology, Low power CMOS design, Optical computing etc. This paper presents two design approaches for four bit binary combinational shifter circuit with the help of different types of reversible logic gates. The proposed optimized design is simulated using Modelsim tool and synthesised for Xilinx Spartan 3E with Device XC3S500E with 200 MHz frequency
NIOS II Based Secure Test Wrapper Design for Testing Cryptographic Algorithms
Get PDFCryptographic algorithms need infrastructure for testing them against security attacks. Normally many methods are proposed for testing these cryptographic primitives. Normal designs cannot be applied to all types of cryptographic chips. Usually build in self test is applied for the intellectual property chips for testing them. But it suffers from many problems such as side channel attack, backholes, high area overhead, etc.., to overcome all these drawbacks test wrapper is designed and tested using NIOS II economy soft core processor. NIOS II is utilized as the soft core processor and cryptographic algorithms are executed. RTL view of these cryptographic circuits is described. Synthesis result shows the chip planner view of the circuits and the area required for the logic elements. NIOS II soft-core processors perform well for testing the cryptographic algorithms. Results with respects to area optimization, memory and speed are discussed. The logic components required for design using NIOS II is optimized. Memory required is also less compare to other processors. Area required is optimized using NIOS II processor and it is flexible for design of complex circuits
Design and Development of Low Cost Navigation and Security System for Indian Fisherman Using Adrino Nano Platform
Get PDFThe fishing industry plays a major role in development of Indian economy. The recent attacks on fishermen taking place in Indo-Srilanka and Indo-Pakistan maritime boundaries have been major concerns. These attacks are primarily caused by the lack of navigation and security features during the voyage. Hence the current situation demands the implementation of precise facilities for reducing man and material loss. This project involves the design and implementation of a Low cost Navigation and Security System for Indian fishermen on Arduino Nano platform. The system developed solves the above said issues by continously tracking the location of fishing vessel and providing minimal security features. The system ensures that navigation is in safe zone within the nation’s maritime boundary and also prevents crossover. This is acheived using GPS receiver which directly links to GPS satellites for current location of the vessel. The required data fields like the latitude and longitude data along with the time stamps are extracted from the GPS samples and used for comparision for determining the exact location of the vessel. This procedure will help in detection of corner cases when the vessel is nearing or about to crossover the maritime boundary, which cannot be marked physically. It is useful for triggering conditions like enabling or disabling fuel injection system, the warning beeps and display notifications to the fishermen. Manual override facility for restarting the engine in case of crossover for limited duration is provided. The security features like authentication for the genuine operator to get access to the engine panel, the support for distress message and the storage of the exact time stamps and GPS locations after encryption in case of initiation of transmitting distress message is provided as a blackbox feature. The passcode based mechanism allows for maximum of three attempts to unlock access to control panel. The GSM modem allows for transmission of distress message to the registered base station/coast guard. The encrypted GPS samples and time stamps are stored in on-chip EEPROM memory for future reference.
Real-Time Algorithms and Architectures for several user Channel Detection in Wireless Base Station Receivers
Get PDFIn this paper presents algorithms and architecture designs that can meet real-time requirements of for several user channel estimation and detection in code-division multiple-access-based wireless base-station receivers. Entangled algorithms proposed to implement several user channel assessment and demodulation make their real-time execution difficult on current digital signal processor-based receivers. A based several user channel assessment scheme requiring matrix conversion is draft again from an demodulation perspective for a reduced intricacy, repetitive scheme with a simple fixed-point very large scale integration architecture. A reduced-intricacy, bit-streaming several user demodulation algorithm that avoids the need for demodulation is also developed for a simple, pipelined VLSI architecture. Thus, we develop real-time solutions for several user channel assessment and demodulation for third-generation wireless systems by: 1) designing the algorithms from a fixed-point execution perspective, without significant loss in error rate performance; 2) task partitioning; and 3) designing bit-streaming fixed-point VLSI architectures that explore pipelining, correspondence, and bit-level computations to achieve real-time with minimum area overhead