International Journal of Reconfigurable and Embedded Systems (IJRES)
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Online Self-testable Multi-core System using Dynamic Partial Reconfiguration of FPGA
Get PDFThis paper presents a novel and efficient method of designing an online self-testable multi-core system. Testing of a Core Under Test (CoUT) in a massively multi-core system can be carried out while the system is operational, by assigning the functionality of the CoUT to one of the non-functioning/idle and pre-tested core. The methodology presented in this paper has been implemented taking a test setup by demonstrating the Dynamic Partial Reconfiguration (DPR) feature of latest FPGAs on Zynq-7 XC702 evaluation board. The simulation results obtained from the experimental setup show that the utilization of a multi-core system can be significantly improved by effectively utilizing the idle core(s) to back up CoUT(s) for on-line test without a significant hardware overhead and test latency
Design Considerations of Reconfigurable CMOS Mixers for Multi-Standard Communication Receiver Systems
Get PDFThis paper has been carried out the study of reconfigurable wide-band mixers that can do the frequency conversion and gain variation standards with low noise and high linearity used in multi-mode and multi-standard receivers. Over the last few years reconfigurability has become very popular in adopting technology to meet the wideband wireless communication specifications that is compatible with multi-standards like GPS (1.57 GHz), WLAN (2.4 GHz - 5.9 GHz), Bluetooth (2.402 – 2.483 GHz) and ZigBee (0.784 - 0.915 GHz) in low power consumption environment. The reconfigurability can be achieved between low and high band modes through power switching in RF frequency mixers. It can be achieved by flipping the input RF signal between gate and source terminal of input transistor and altering the trans-impedance stage output. With the concept of reconfigurable transistor pair with open and short circuit stubs, one can not only find the configurable gain with center frequencies 7.355, 8.65, 11.35 and 12.65 GHz but also with high power efficiency. Tow Thomas Bi-Quad Topology other than the traditional current commuting technique for the second order trans-impedance amplifier stage, works as a current mode filter over a tunable bandwidth. The active Gilbert mixers are used widely in most of communication system, due to its significance gain, perfect isolation, and linearity in response
FPGA Based Symmetrical Multi Level Inverter with Reduced Gate Driver Circuits
Get PDFMultilevel converters tender advantages in terms of the output waveform quality due to the increased number of levels used in the output voltage modulation and have been widely accepted for high-power high-voltage applications. This paper introduces topology in multilevel dc link inverter (MLDCLI), which can significantly reduce the switch count and improve the performance. The preferred topology provides a dc voltage with the shape of a staircase approximating the rectified shape of a commanded sinusoidal wave, to the bridge inverter, which in turn gives the required alternating waveform. This topology requires fewer components compared to traditional Multi level Inverters (MLI).Therefore, the overall cost and complexity are significantly reduced particularly for higher output voltage levels. Finally, Matlab/Simulink and XILINX are used as a simulation and compiler architecture of control circuit embedded in FPGA. Simulation and experimental results for fifteen-level inverter are presented for validation
FPGA Implementation of High Speed Hardware Efficient Carry Select Adder
Get PDFThis paper presents a novel architecture for high speed and hardware efficient carry select addition. We modify the two operand ripple carry addition followed in conventional Carry SeLect Adder(CSLA) with a simple and efficient gate level circuit to reduce area and delay significantly. For this, we use an increment 1 block for generating the sum outputs with carry input 1 instead of second pair ripple carry adder as in conventional CSLA. The novelty of the proposed approach is that it reduces area, and the delay due to carry propagation in second pair of adder cells. The proposed CSLA adder has been designed using structural VHDL code and synthesized using Altera Quartus II. Experimental results show that the proposed design outperform the previous approaches in terms of delay and area reduction
MEMS Seismic Sensor with FPAA Based Interface Circuit for Frequency-Drift Compensation using ANN
Get PDFElectrochemical MEMS seismic sensor is limited by its non-ideality of frequency dependent characteristics hence interface circuits for compensation is necessary. The conventional compensation circuits are limited by high power consumption, bulky external hardware circuitry. In these methods digital circuits are also limited by inherent analog to digital conversion and vice versa which consumes significant power, acquires more size and limits speed. A Field programmable analog array (FPAA) overcomes these limitations and gives fast, simple and user friendly development platform with less development speed comparable to ASIC. Recently FPAA becoming popular for rapid prototyping. The proposed system presents FPAA (Anadigm AN231E04) based hardware implementation of ANN model. Using this FPAA based compensation circuit, the error in frequency drift have been minimized in the range of 3.68% to about 0.64% as compared to ANN simulated results in the range of 23.07% to 0.99 %. This single neuron consumes of power of 206.62 mW. and has minimum block wise resource utilization. The proposed hardware uses all analog blocks which remove the requirement of ADC and DAC reducing significant power and size of interface circuit. This work gives the SMART MEMS seismic sensor with reliable output and ANN based intelligent interface circuit implemented in FPAA hardware
NOC Based Router Architecture Design Through Decoupled Resource Sharing Using CABHR Algorithm
Get PDFA Network-on-Chips (NoCs) is rapid promising for an on-chip alternative designed in support of many-core System-on-Chips (SoCs). In spite of this, developing an increased overall performance low latency Network on chip using low area overhead has always been a new challenge. Network on Chips (NoCs) by using mesh and torus interconnection topologies have become widely used because of the easy construction. A torus structure is nearly the same as the mesh structure, however, has very slighter diameter. In this regard, we propose effective router design for Decoupled Resource sharing in a torus topology based on clustering algorithms Based Hierarchical Routing (CABHR) to get better the efficiency of NoC. We show that our approach is provides improved latency and energy consumption, overall performance developments compared to the most distinguished existing routing techniqu
Design and Implementation of LCG-Trivium Key Stream Generator into FPGA
Get PDFThis paper presents the Design and implementation into Field ProgrammableGate Array (FPGA) of a combine stream cipher and a simple linear congruential generator circuit to produce key stream. The LCG circuit is used to produce initialization vector (IV) each 264 clock cycle to the cipher trivium in other to strengthen the complexity of the cipher to known attacks on trivium. The LCGTrivium is designed to generate 2144 bits of keystream from an 80-bits secret and a variable 80-bits initial value. To implement the LCG-Trivium on FPGA, we use VHDL to build a simple LCG and Trivium and a state machine to synchronize the functioning of the LCG and Trivium. The number of gates, memory and speed requirement on FPGA is giving after analysis. The design is simulated, synthesized and implemented in Quartus II 10.1, ModelSim-Altera 6.5 and Cyclone IV E EP4CE115F29C7N
FPGA based Implementation of Symmetrical Reduced Switch Multilevel Inverter
Get PDFMultilevel inverter has become more popular and attractive for drive applications. Among the various modulation techniques, Carrier based techniques has been commonly used because of their simplicity and flexibility. This paper presents the comparisons of bipolar multicarrier pulse width modulation for the new symmetrical multilevel inverter. The performance parameters of new multilevel inverter were analyzed through various switching strategies. The detailed study has been carried out by MATLAB/SIMULINK. The real time implementation was carried out using FPGA. The results of both simulation and experimentation were compared
Application of Inverse Perspective Mapping for Advanced Driver Assistance Systems in Automotive Embedded Systems
Get PDFIn the recent times vehicle manufactures and automotive suppliers are progressing towards building vision based subsystems for provisioning driver assistance while targeting the automotive safety critical needs. While the acquired images constitute the fundamental input for any vision based system, transforms on images become essential to derive and gain insight into certain specific features. These derived features are used and reused at multiple places for varied automotive applications. This situation warrants a scalable and flexible image processing platform for a class of automotive applications. An attempt is made in this Research work to propose architecture that, specially, includes a layer of image transformations and to implement a prototype image processing platform. Inverse Perspective Mapping (IPM), a widely used class of transforms is emphasized in the present architecture alongside other nominal transforms. Lane departure warning system is implemented on this platform for the purpose of illustration and to analyze the effectiveness of the proposed architectur
Notice of Retraction Designing of Vedic Based Modulo Multiplication in Residue Number System
No full textNotice of Retraction-----------------------------------------------------------------------After careful and considered review of the content of this paper by a duly constituted expert committee, this paper has been found to be in violation of IAES's Publication Principles.We hereby retract the content of this paper. Reasonable effort should be made to remove all past references to this paper.The presenting author of this paper has the option to appeal this decision by contacting ijres@iaesjournal.com.-----------------------------------------------------------------------Residue Number System (RNS) is a very old number system which was proposed in 1500 AD. Parallel nature for mathematical operations in RNS results in faster computation. This paper deals with designing of modulo multiplication in RNS. Direct computation of |AB|m, requires multiplier to get A.B first and then Mod-m calculator to get the final result. We have used Vedic technique along with RNS to improve the computation time for modulo multiplication. This paper is aimed at designing and analysis of modulo multiplier for special moduli set like 3, 5 and 7. Comparative analysis in terms of area and delay is performed for input data size (N=8, 16 and 32-bit) between proposed technique and direct computation using Xilinx ISE 14.1. Design is also been compared using Synopsys Design Compiler with 32 nm Std_Cell Library. It is found that proposed technique is more efficient in terms of speed when input data size increases