International Journal of Reconfigurable and Embedded Systems (IJRES)
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A Power Efficient Self Biased OTA Design Based on g_m/I_D Methodology with Considering Load Variation, Temperature Variation and Power Supply Variation
Get PDFThe present work addresses the design of power efficient fully self biased OTA using a design methodology based on the transistor characteristics. This analog module was analyzed, designed and prototyped in TSMS 0.35μm CMOS technology. Simulation results are presented, in order to validate the methodology. The OTA has Gain of 41.35 dB and 3db bandwidth of 138.73 kHz and the UGB of 12.40MHz with the current consumption of 65.50 μA. The circuit does not have need of any DC external biasing circuit, only need to apply VDD (3.3 V). Here self biasing has been introduced with power consumption of 216.15μW. The results have been taken with load variations, temperature variations, and power supply variations. This circuit used in real time high frequency applications as in RF communication
Real time FPGA Implementation of PWM Chopper Fed Capacitor Run Induction Motor
Get PDFThis paper presents the performance enhancement of capacitor run induction motor by pulse width modulated AC chopper.The phase angle control faces severe shortfall in the performance improvement for larger triggering angles. In this paper the comparison of phase angle control and sinusoidal pulse width modulation technique is encountered for effective speed control of single phase capacitor run induction motor. The necessary parameters are taken into considerations are higher efficiency, lesser total harmonic distortion and high input power factor. The results are compared by using the simulations using matlab Simulink environment. The validation of result in hardware is implemented using Field programmable gate array for sinusoidal pulse width modulation technique
Thermal Analysis of Fair Scheduling in Real-time Embedded Systems
Get PDFOver the past few decades, increased demand of highly sophisticated real-time applications with complex functionalities has directly led to exponentially increased power consumption and significantly elevated system temperatures. These elevated temperature and thermal variations present formidable challenges towards system reliability, performance, cooling cost and leakages. This article explores the thermal management strength of two fairness based algorithms, namely Proportional Fair (PFair) and Deadline Partitioning Fair (DP-Fair). In related literature, the introduction of fairness is often considered as a tool to achieve optimality in multiprocessor scheduling algorithms. This work shows that these algorithms bring about better thermal profile when compared with the commonly used Earliest Deadline First (EDF) algorithm in similar conditions both in uniprocessor and multiprocessor environments. A simulation is conducted for periodic task set model. The obtained results are encouraging and show that use of fairness based algorithms reduces the operating temperature, peak temperature, and thermal variations
Implementation of High Speed Vedic Multiplier Using Vertical and Crosswise Algorithm
Get PDFMultiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate (MAC) and inner product are some of the frequently used operations in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors in its arithmetic and logic unit. Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications. In this project, the comparative study of Vedic multiplier and Sequential multiplier is done for low power requirement and high speed. The proposed architecture is based on the Vertical and Crosswise algorithm of ancient Indian Vedic Mathematics, which increases the speed of multiplier by reducing the number of clock cycles thus achieving the greater speed of the processor or system
Design and Implementation of a New Architecture of a Real-Time Reconfigurable Digital Modulator (DM) Into QPSK, 8-PSK, and 16-PSK on FPGA
Get PDFOne of the prerequisites of Electronic Warfare (EW) is to have the means to provide secure point-to-point wireless data and voice communications with other ground stations. New technologies are giving rise to bigger information security threats. This situation illustrates the best the urgency of reducing the development and upgrade time of EW systems. Previous works suggest that digital systems are the best candidates for this purpose and therefore form the backbone of modern Electronic Warfare. Indeed, Digital Modulation (DM) techniques are widely used in modern wireless communication systems. This is largely due to their high resistance to noise and their high transmission capacity that can be achieved through data multiplexing. In this article, a new reconfigurable architecture of a Phase Shift Keying (PSK) modulation is described. The latter can be configured in real time to produce the following modulation schemes: QPSK, 8-PSK, and 16-PSK without having to regenerate the FPGA configuration bits. This action can be done by software via programming or manually using a DIP switch. The proposed design is implemented on the Xilinx xc7k325tfbg900 FPGA using the Genesis 2 development board. The Vivado Physical Design Automation tool indicates a power consumption of 303 mW by the on-chip circuit. The experimental results are in agreement with the simulations
FPGA Implementation of DTCWT and PCA Based Watermarking Technique
Get PDFThe hardware implementation of the image watermarking algorithm offers numerous distinct advantages over the software implementation in terms of low power consumption, less area usage and reliability. The advantages of Dual Tree Complex Wavelet Transform (DTCWT) and Principle Component Analysis (PCA) techniques are extracted to improve the robustness and perceptibility. The hardware watermarking solution is more economical, because adding the component only takes up a small dedicated area of silicon. The algorithm is developed and simulated using Matlab, Simulink and system generator. The implementation is carried out using Spartan 6 Diligent Atlys Field Programmable Gate array (FPGA). The architecture uses 256 slice registers, 257 slice Look Up Tables (LUT’s) and 47 I/O pins. It also meets the requirement of high speed architecture with a delay of 1.328ns and an operating frequency of 549.451MHz
Minimizing the loses of solar power generation by designing an intelligent tracking system implemented on FPGA
Get PDFThe increasing of using of an electrical power as a power source in a large number of devices can occur a serious problem in our daily life. One of the useful power sources is a solar cell which used to overcome many problems of power generation. In this paper, the solar cell model is proposed to minimize loses of solar power generation by designing of an intelligent tracking system based on FPGA. PSO algorithms are used to train the neural networks to control the speeds and the directions of rotations of two DC motors with the help of FPGA cart. The proposed system was implemented in MATLAB; and for the hardware part, FPGA was used for the implementation of neural networks
Berger Code Based Concurrent Online Self-Testing of Embedded Processors
Get PDFIn this paper, we propose an approach to detect the temporary faults induced by an environmental phenomenon called single event upset (SEU). Berger code based self-checking checkers provides an online detection of faults in digital circuits as well as in memory arrays. In this work, a concurrent Berger code based online self- testable methodology is proposed and integrated in 32-bit DLX Reduced Instruction Set Computer (RISC) processor on a single silicon chip. The proposed methodology is implemented and verified for various arithmetic and logical operations of the DLX processor. The FPGA implementation of the proposed design shows that a meager increase in hardware utilization facilitates online self- testing to detect temporary faults
An Optimal Design of CMOS Two Stage Comparator Circuit using Swarm Intelligence Technique
Get PDFA swarm intelligent based optimization technique named as Flower pollination algorithm (FPA) is applied for the design of the CMOS two stage comparator circuit. The basic idea of FPA mimics the flower pollination process of flowering plants. The input control parameters of FPA improve the exploration and exploitation capabilities of optimization problem. This paper presents the design of a CMOS two-stage comparator circuit using simulation based model called swarm intelligence technique. Simulation results shows that the proposed method is capable to determine the transistor sizes and bias current values of the CMOS comparator. The results obtained from the FPA improved the design performance of comparator in terms of power consumption, MOS transistor area and gain. To investigate the efficiency of proposed approach, comparisons have been carried out with differential evolution (DE) and harmony search (HS) algorithm based circuit design. The performances of FPA based comparator design are better than the previously reported work
Analysis of CMOS Logic and Transmission Gate for 64 Bit Parallel Prefix Adders
Get PDFParallel prefix adder network is a type of carry look ahead adder structure. It is widely considered as the fastest adder and used for high performance arithmetic circuits in the digital signal processors. In this article, an introduction to the design of 64 bit parallel prefix adder using transmission technique which acquires least no of nodes with the lowest transistor count and low power consumption is presented. The 64 bit parallel prefix adder is designed and comparison is made between other previously parallel prefix adders. The result shows that the proposed 64 bit parallel prefix adder is slightly better than existing parallel prefix adders and it considerably increases the computation speed.The spice tool is used for analysis with different supply voltages