International Journal of Reconfigurable and Embedded Systems (IJRES)
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Automated smart car parking system using raspberry Pi 4 and iOS application
Get PDFIn interconnection and automation of different physical gadgets, vehicles, home machines and different things, the internet of things (IoT) innovation plays a critical role. These objects associate and deal information with the assistance of software, different sensors, and actuators. A human's standard of life and living are improved with this automation of gadgets, which is a forthcoming need. In this paper we talked about a similar requirement for instance, a smart car parking system which empowers a driver to discover a parking area and a free slot in that parking area inside a city. This paper focus on decreasing the time squandered on discovering parking area. This in turn diminishes the fuel utilization and way of life. With the exponential increment in the quantity of vehicles and total population, vehicle accessibility, use out, about starting late, finding a space for parking the vehicle is turning out to be increasingly more troublesome with realizing the amount of conflicts, for example, automobile overloads. This paper is connected to making a trustworthy system that accept authority over the undertaking of recognizing free slots in a parking area and keeping the record of vehicles left in an extremely methodical way. The predicted system decreases human effort at the parking area generally, for example, in case of looking of free slots by the driver and calculating the portion for each vehicle using parking area. The different advances engaged with this system are vehicle unique proof utilizing RFID labels; free slot discovering utilizing Ultrasonic sensors and payment count is done based on time of parking
Effect of integrated power and clock networks on combinational circuits
Get PDFReduction of power consumption is necessary in a system on chip. To achieve this, power and clock networks can be integrated. This leads to a significant reduction in power consumption in a circuit. This paper explores the effect of such a network on various combinational circuits and compares the power consumption of these circuits with conventional combinational circuits. The combinational circuits which are powered by the proposed circuit consume lesser power as compared to conventional combinational circuits
Dynamic modeling of the birefringence effects induced in semiconductor optical amplifier for all-optical telecommunication systems
Get PDFThe semiconductor optical amplifiers (SOA) are all-optical multifunctional devices. The improvement of their performance will, therefore, be of great importance for modern optical telecommunication systems. We propose in this article to develop a dynamic model that enables us to simulate the dynamic behavior of SOA's birefringence effects. The determination of a numerical model is a multidisciplinary activity that needs engineering skills, optimization and physics. This numerical model enables to describe the propagation of a picosecond optical pulse passing through the SOA and takes into account its polarization and the phenomenon of energy coupling between the eigenmodes of SOA (TE mode and TM mode). In this paper, we will, first of all describe the numerical algorithm of our model, and then we will propose to make a dynamic characterization of the effect of the nonlinear polarization rotation in the SOA, which will allow us to study the all-optical logic gates as well as all the other digital components based on the nonlinear effect of birefringence in SOA
Modern design approach of faults (toggling faults, bridge faults and SAT) of reduced ordered binary decision diagram based on combo & sequential blocks
Get PDFIn this Research we are going to develop ROBDD (Reduced Ordered Binary Decision Diagram) designs to detect toggling faults, bridge faults and SAT (Stuck at Fault), Here we are going to develop sequential blocks using ROBDD and applying to the mux to detect stuck at faults and also connecting the combo & Sequential blocks to find the toggling faults by connecting or using automatic test pattern generator. In this research we are going to develop the bridges between the blocks of ROBDD designs and converting them to and or logic to find the bridge faults of the design. Finding bridge and toggle faults are more difficult in logic designs, here we use an advance technique to find the faults of the design by calculating the path delays of the individual blocks of the design. More concentrating on the path delays by using basic stuck at faults methods to refer the faults (toggling and bridge faults) at mux output. In our research the basic design modules are ROBDD circuit of both combinational and sequential blocks are designed and tested using Multiplexer and K-map Simplification Methods. The main purpose of the research to find the faults at all levels of all logic designs which involves in both combinational and sequential blocks of the design
Low power 11T adder comparator design
Get PDFComparator is a basic arithmetic component in a digital system and adders are the basic block of processor unit, the performance of adder will improve the system performance. The proposed 11T adder comparator is consists of three main components, namely XOR, inverter, and MUX logic. The circuit is designed and implemented based on top-down approach with 11 transistors. The proposed cell can be used at higher temperature with minimal power loss. It also gives faster response for the carry output. The proposed comparator circuit shows 63.80% improvement in power consumption than other circuits
Design and analysis of different full adder cells using new technologies
Get PDFCMOS transistors are most widely used for the design of computerized circuits, when scaling down the nanometer technology these devices faces the short channel effects and causes I-V characteristics to depart from the traditional MOSFETs, So the researchers have developed the other transistors technologies like CNTFET and GNRFET. Carbon nanotube field effect transistor is one of the optimistic technologies and it is a three terminal transistor similar to MOSFET. The semiconducting channel between the two terminals called source and drain comprises of the nano tube which is made of carbon. Graphene nano ribbon filed effect transistor is the most optimistic technology here the semiconducting channel is made of graphene. When contrasted with barrel shaped CNTFETs, GNRFETs can be prepared in situ process, transfer-free and silicon compatible, thus have no passage related and alignment problems as faced in CNTFET devices. This paper presents different 1-bit Full Adder Cells (FACs) like TG MUX-based FAC (TGM), MN MUX-based FAC (MNM), proposed TG Modified MUX-based FAC (TGMM) and another proposed MN Modified MUX-based FAC (MNMM) are designed using different technologies like CNTFET and GNRFET at 16nm technology with supply voltage of 0.85v and simulation is done by using Synopsys HSPICE Tool and the proposed designs are best when compared to the TGM and MNM FACs in terms of Static and Dynamic powers Dissipations and Delay
A hardware system with ARM-based data processing for nano satellites
Get PDFThe Institute of Scientific and Technical Research for Defense in Argentina (Instituto de Investigaciones Científicas y Técnicas para la Defensa - CITEDEF) is developing a processing hardware module based on a ARM Cortex M4 processor from STMicroelectronics. The microcontroller (MCU) has the capacity to run at a maximum clock frequency of 180 MHz, integrates a Floating Point Unit (FPU). An 8MB SDRAM was included for dynamic data allocation. This hardware will host and process the algorithms to calculate and determine the nanosatellite’s attitude. The module is intended to be Cubesat compatible, possess a flexible design, handles various inertial sensors and can manage backups on microSD memory cards with sizes up to 32GB
Data ecryption based on multi-order FrFT, and FPGA implementation of DES algorithm
Get PDFCryptography techniques need some algorithms for encryption of data. Most of available encryption techniques are used for textual data; a few of encryption methods are used for multimedia data; However, This Algorithms that are used for textual data may not be inefficient for multimedia, because it is size is greater than the text. Therefore, Cryptosystems need to find and develop a new encryption schemes for such data. The most popular symmetric key algorithms are Data Encryption Standard (DES). However, DES is may be not suitable for multimedia because it consumes times. Encryption and decryption of these data require different methods. In this paper a method for encryption/decryption data by using the nature of FrFT in signals analysis, based on multi-order Fractional Fourier Transform has been introduced. The security of the method used in the encryption work was taken into account to identify the different indicators to measure the security of the encryption Techniques. These indicators are: sensitivity proposed Techniques for the key, the complexity of the processes, and statistical analysis. The key is formed by combination of order of Fractional Fourier Transform. The encrypted data is obtained by the summation of different orders. Numerical simulation results are given to demonstrate this proposed method
6 Transistors and 1 memristor based memory cell
Get PDFArea efficient and stable memory design is one of the most important tasks in designing system on chip. This research concentrates in designing a new type of hybrid memory model by using only nMOS transistors and memristor. The proposed memory cell is very stable during successive read operates and comparatively faster and also occupies less amount of silicon area. The stability of the data during successive read operation and noise margin are in the promising range. Extensive simulation results using LTspice and Cadence software tools demonstrate the validity and competency of the proposed model
Approximate arithmetic circuits
Get PDFLow power consumption is the necessity for the integrated circuit design in CMOS technology of nanometerscale. Recent research proves that to achieve low power dissipation, implementation of approximate designs is the best design when compared to accurate designs. In most of the multimedia applications, DSP blocks has been used as the core blocks. Most of the video and image processing algorithms implemented by these DSP blocks, where result will be in the form of image or video for human observing. As human sense of observation is less, the output of the DSP blocks allows being numerically approximate instead of being accurate. The concession on numerical exactness allows proposing approximate analysis. In this project approximate adders, approximate compressors and multipliers are proposed. Two approximate adders namely PA1 and PA2 are proposed which are of type TGA which provides better results like PA1 comprises of 14 transistors and 2 error distance, achieves reduction in delay by 64.9 % and reduction in power by 74.33% whereas the TGA1 had 16 transistors and more power dissipation.PA2 comprises of 20 transistors and 2 error distance. Similarly PA2 achieves delay reduction by 51.43%, power gets reduced by 67.2%. PDP is reduced by 61.97 % whereas TGA2 had 22 transistors. An Approximate 4-2 compressor was proposed in this project to reduce the number of partial product. The compressor design in circuit level took 30 transistors with 4 errors out of 16 combinations whereas existing compressor design 1 took 38 and design 2 took 36 transistors. By using the proposed adder and compressors, approximate 4x4 multiplier is proposed. The proposed multiplier achieves delay 124.56 (ns) and power 29.332 (uW) which is reduced by 68.01% in terms of delay and 95.97 % in terms of power when compared to accurate multiplier