International Journal of Reconfigurable and Embedded Systems (IJRES)
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A compact graphene based nano-antenna for communication in nano-network
Get PDFDue to recent advances in nanotechnology, the use of nano-devices and its network becomes more popular in the field of medical, commercial and military applications. One of the major issues in designing nano-network is miniaturization of nano-devices which are limited due to communication antenna used in that device and its power constraints. At 1000nm size, an antenna resonates at around 100 THz which suffers from greater propagation loss and provides signal coverage of micrometer distances. Hence there is a need for nano-antenna with reduced size and also operating at mid infrared frequencies to provide a good signal coverage. In this paper, graphene-based nano-antenna is presented. The model resonates at 55THz frequency with a peak gain of 5.47 dB in the propagation direction. The model exploits the principle of surface plasma polarition waves for miniaturization and achieves 50% size reduction when compared to conventional nano-antenna and best suitable for nano-network communications
Implementation of PWM AC chopper controller for capacitor run induction motor drive via bacterial foraging optimization algorithm
Get PDFThis paper focuses on design of closed-loop control for pulse width modulated AC chopper controlled capacitor run induction motor drive engaging enriched optimization algorithm based on foraging of bacteria. Capacitor run induction motor is a non-linear device and its parameter varies under different functional point of the system. A linearized increment model for PWM AC chopper is illustrated for a particular functional point of the drive. The conventional method does not provide acceptable performance under different load conditions. Bacteria foraging optimization technique categorizes accurate control parameters for the superlative dynamic response under unit step load variations. Field Programmable Gate Array is implemented practically for a particular functional point of the drive to exhibit accurate performance. Experimental and simulated results are obtained to authenticate the effectiveness of the optimized controller.
Quadcopter based emergency medikit delivery system for hill stations
Get PDFNowadays UAV’s are more common for search, rescue and surveillance. A quadcopter UAV system is proposed to be used for aerial transportation of medicine. A Quadcopter has a drive chassis having a propeller, ESC, motor, frames and battery. The quadcopter is supported with GPS to know the exact position. To know the exact location and delivering medicine to accident area, an audio and video system is used. The quad frame built from quality materials, which are reinforced and much more stronger, this reduces arm breakage. A set of two plastic propellers, one normal and one pusher (reverse) to rotate and lift up the quadcopter. The brushless out-runner will provide more power with its high efficiency, long run times. The ESC includes programmable motor braking, soft start for helicopters and planes, timing, throttle input range and low-voltage cutoff. Lithium-Polymer (Li-Po) battery for very lightweight, small size and durability without losing charging capacity. The whole quadcopter process can be monitored and controlled by a remote control system, quadcopter will capture the live video and current status can be seen visualized and provides information about all the other exact conditions in real-time
Application of optimal artificial intelligence based tuned controllers to a class of embedded nonlinear power system
Get PDFThis paper studies the implementation of the Bat Inspired Algorithm (BIA) as an optimization technique to find the optimal parameters of two classes of controllers. The first is the classical Proportional-Integral-Derivative (PID). The second is the hybrid fractional order and Brain Emotional Intelligent controller. The two controllers have been implemented, separately, for the load frequency control of a single area electric power system with three physical imbedded nonlinearities. The first nonlinearity represents the generation’s rate constraint (GRC). The second is owing to the governor dead band (GDB). The last is due to the time delay imposed by the governor-turbine link, the thermodynamic process, and the communication channels. These nonlinearities have been embedded in the simulation model of the system under study. Matlab/Simulink software has been applied to obtain the results of applying the two classes of controllers which have been, optimally, tuned using the BIA. The Integral of Square Error (ISE) criterion has been selected as an element of the objective function along with the percentage overshoot and settling time for the optimum tuning technique of the two controllers. The simulation results show that when using the hybrid fractional order and Brain Emotional Intelligent controller, it gives better response and performance indices than the conventional Proportional-Integral-Derivative (PID) controllers
Surface potential modeling of dual metal gate-graded channel-dual oxide thickness with two dielectric constant different of surrounding gate MOSFET
Get PDFAn Analytical study for the surface potential, threshold voltage and Subthreshold swing (SS) of Dual-metal Gate Graded channel and Dual Oxide Thickness with two dielectric constant different cylindrical gate surrounding-gate (DMG-GC-DOTTDCD) metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed to investigate short-channel effects (SCEs). The performance of the modified structure was studied by developing physics-based analytical models for the surface potential, threshold voltage shift, and Subthreshold swing. It is shown that the novel MOSFET could significantly reduce threshold voltage shift and Subthreshold swing, can also provides improved electron transport and reduced short channel effects (SCE). Results reveal that the DMG-GC-DOTTDCD devices with different dielectric constant offer superior characteristics as compared to DMG-GC-DOT devices. The derived analytical models agree well with simulation by ATLAS
Two state-of-the-arts current-mode ternary full adders based on CNTFET Technology
Get PDFAdder core respecting to its various applications in VLSI circuits and systems is considered as the most critical building block in microprocessors, digital signal processors and arithmetic operations. Novel designs of a low power and complexity Current Mode 1-bit Full Adder cell based on CNTFET technology has been presented in this paper. Three major parts construct their structures; 1) the first part that converts current to voltage; 2) threshold detectors (TD); and 3) parallel paths to convey the output currents flow. Adjusting threshold voltages which are significant factor for setting threshold detectors switching point has been achieved by means of CNTFET technology. It would bring significant improvements in adjusting threshold voltages, regarding to its unique characterizations. Simple design, less transistor counts and static power dissipation and better performance comparing previous designs could be considered as some advantages of the novel designs
Design and implement of high gain and low noise neural amplifier using compensation techniques
Get PDFElectroencephalography is refer to record the electrical signal with respect to brain activity and its reliable EEG information, using this to diagnosis disorder and tumors. However the signal is very difficult to capture and processing due to so many parameter. Mainly this signal is very low range that from 0.1 to 100μv in and its bandwidth range from 1Hz to 100 Hz. So the signal has amplified by using linear and accurate digital program amplifier(PGA).This amplifier has been designed by using First stage amplifier with gain of 120dB with low output noise. The PGA is consists of OPAMPs the PGA change from 10 dB to 120dB.Inorde to optimized the linear and gain accuracy a new structure resister array is proposed high gain PGA. Hence the simulated result has shown it is promising to exhibit an amplifier with high performance biomedical application
Low power and high performance FFT with different radices
Get PDFFFT is one of the most active blocks in digital signal processing and in various field of communication systems. FFT has received significant attention over the past years to increase its capability and versatility. This paper describes an extensive study on trade-off of different radices with different computational elements of butterfly such as adders and multipliers. Finding an efficient radix along with computational elements is the key point to find best suite i.e. high precision, low power and low area applications like radar, filtering, image compression etc. The work also considers the precision and the data format to represent constant value such as Q-point. The proposed FFT architectures not only uphold better solutions for low power and high-performance application systems, but also open up a new research lines. This paper demonstrates that radix-2^3 consumes 43% less LUTs and 17% less power consumption, 40% increase of frequency in radix-2^2 in comparison with radix- 2 algorithm for the combination of CSA with modified booth multiplier and the increment of frequency about 19%, 26% less LUTs consumption and 26% less power in Radix-2^2 when compared to radix-4 with various combination of adder and multiplier. In this work we have used Xilinx 14.7 XST for synthesis and the target device used is Spartan6 XC6SLX100. Simulation is carried out in Xilinx ISIM and also performed timing analysis and generated post-place and route
Energy and Area Effective Hardware Design of Lifting Approach Discrete Wavelet Transform
Get PDFThis paper presents low power Discrete Wavelet Transform DWT architecture, comprising of forward and inverse multilevel transform for 5/3 lifting scheme LS based wavelet transform filter. This LS filter consists of integer adder units and binary shifter rather than multiplier and divider units as in the convolution based filters; hence it is more adaptable to energy efficient hardware performance. The proposed architecture is described using the VHDL based methodology. This VHDL code has been simulated and synthesized to achieve the gate level building design which can be organized to be effectively developed in hardware environment. The Quartus II 9.1 software synthesis tools were employed to implement 2D-DWT VHDL codes in Altera Development board DE2, with Cyclone II FPGA device. The proposed LS wavelet architectures can be attained by focusing on the physical FPGA devices to considerably decrease the needed hardware expenditure and power consumption of the design. The utilized logic and register elements of the architecture are 127 slices (only 1%) usage from 33216 and the architecture consumes only 0.033 W. Simulations were performed using different sizes of gray scale images that authenticate the proposed design and attain a speed performance appropriate for numerous real-time applications
Design of a 60 GHz power amplifier in a 45nm CMOS
Get PDFThis Paper presents a design and implementation of class-AB power amplifier which works at 60GHz unlicensed frequency band. This power amplifier uses a MOSFET from gpdk45 technology library. The design simulation is done by cadence Analog Design Environment. This proposed power amplifier yields a power added efficiency of 23.45% and a power gain S21 of 10dB at 60GHz. The output impedance of proposed power amplifier is needs to be matched with 73Ω antenna impedance. The S22 output matching of the simulated power amplifier is -18dB at 60GHz. The input side is matched to arbitrary impedance of 50Ω the resulting S11 of simulated result is noted to be -15dB at 60GHz. The proposed circuit has a noise figure of 3.85dB. The proposed circuit has a Pout-1dB of 8.5dBm. the designed class AB power amplifier is an important component in 60GHz transceiver. The layout of the associated circuit is drawn with the total size of 0.107um2