International Journal of Reconfigurable and Embedded Systems (IJRES)
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Design and Implementation of Reduced Power Energy Efficient Binary Coded Decimal Adder
Get PDFThis paper presents a novel architecture for low power energy binary represented decimal addition. The proposed BCD adder uses Binary to Excess Six Converter (BESC) block for constant correction to adjusts binary outputs exceeding 9 to correct decimal values and exploits the inherent advantage of reduced delay and switching, due to elimination of long carry propagation in second stage addition as in conventional design and switching OFF of the BESC block for decimal outputs less than 9. The proposed BESC-BCD adder has been designed using VHDL code and synthesized using Altera Quartus II. Experimental results demonstrates that the proposed decimal adder can lead to significant power savings and delay reduction compared to existing BCD adders which is realised in better power-delay product(PDP) performance. For example the PDP saving of the proposed BESC-BCD adder for a 1 digit and 2 digit addition implementations are 11.6% and 16.05% respectively, compared to the best of the designs used for comparison
A low power comparator utilizing MTSCStack, DTTS, and bulk-driven techniques
Get PDFComparator is one of the main blocks that play a vital task in the performance of analog to digital converters (ADC) in all modern technology devices. High-speed devices with low voltage and low power are considered essential for industrial applications. The design of a low-power comparator with high speed is required to accomplish the requirements mostly in electronic devices that are necessary for high-speed ADCs. However, a high-speed device that leads the scaling down of CMOS process technology will consume more power. Thus, power reduction techniques such as multi-threshold super cut-off stack (MTSCStack), dual-threshold transistor stacking (DTTS), a bulk-driven, and a bulk-driven differential pair were studied in this work. This study aims to find and build the combination of these techniques to produce a comparator that can operate in low power without compromising existing performance using the 0.13-µm CMOS process. A comparator with a combination of MTSCStack, DTTS, and NMOS bulk-driven differential pair shows the most promising result of 6.29 µW for static power, 17.15 µW for dynamic power, and 23.44 µW for total power
Restoration circuits for low power reduce swing of 6T and 8T SRAM cell with improved read and write margins
Get PDFThis article clarifies about the variables that influence the static noise margin (SNM) of a static random-access memory. Track down the improved stability of proposed 8T SRAM cell which is superior to conventional 6T SRAM cell utilizing Swing Restored circuit with voltages Q and QB bar are peruse and Compose activity. This SRAM cell strategy on the circuit or engineering level is needed to improve read static noise margin (RSNM), write static noise margin (WSNM) and hold static noise margin (HSNM). This article relative investigation of conventional 6T, standard 8T and proposed 8T SRAM cells with improved stability and static noise margin is finished for 180 nm CMOS innovation. This paper is coordinated as follows: Introduction in area 1, The 6T SRAM cell are portrayed in segment 2. In area 3, proposed 8T SRAM cell is portrayed. In area 4, standard 8T SRAM cell. Segment 5 incorporates the simulation and results which give examination of different boundaries of 6T and 8T SRAM cells and segment 6 conclusions
Performance evaluation of an efficient five input majority gate design in QCA nanotechnology
Get PDFQuantum-dot-cellular-automata (QCA) is the imminent transistor less technology, considered at nano level with high speed of operation and lower power dissipation features. The present paper proposes a novel and an efficient 5-input coplanar majority gate (PMG) with improved structural and energy efficiency. The proposed gate consumes an occupational area of 0.01μm2 with 17 QCA cells which is 50% less in comparison to the best designs reported in literature. The proposed structure is also more energy efficient because it dissipates 21.1% less energy than the best reported designs. The correctness of a proposed majority gate is verified by designing a single bit full adder. The new 1-bit full adder design is structural efficient and robust in terms of gate count and clock delay. It consumes occupational area of 0.05μm2 with 58 QCA cells showing 16.6% improvement in structural efficiency as compared to the best design reported in. It is having a gate count of 4 with the delay of 1 clock cycle. Here, the QCADesigner and QCAPro tools are utilized for the simulation and energy dissipation analysis of proposed majority gate and full adder design
A body bias technique for low power full adder using XOR gate and pseudo NMOS transistor
Get PDFPower dissipation is a major issue in digital circuit design. As technology into developed into range, power and delay becomes vital nanometer parameters to ameliorate the performance of the circuit. To minimize the power consumption many low power techniques such as MTCMOS, stacking, body biasing techniques have been reported. In this paper, a new pseudo NMOS adder circuits have presented. It has designed using transmission gate and body bias technique. Simulation has been accomplished by using SPICE tool. The simulation result show the validity of the proposed techniques is reduces power dissipation from 0.367 mW to 0.267 mW and PDP reduced from 19.311pJ to 13.311pJ. Overall improvement of 29% in power consumption and 30% in PDP has obtained
ACCESS - IoT enabled smart lock
Get PDFACCESS is a centrally controlled extensible security system - a system for enhancing accessibility and security methods. Security is an important matter of concern and everyone wants things easy and fast with the advancement of technology. Many IoT engineers are inclined towards home automation today. An area of recent interest is the automation of lock and key systems of homes and workplaces. This paper comprises mechanisms to view visitors of households, machinery, or any appliance that may be remotely controlled through a mobile application. Owners or supervisors can keep a watch on the guests and choose whom they want to grant entry to. This is conducted by providing the guests with temporary access permission for a validity period of the owner’s choice. They can also simultaneously monitor the activities of the guests
Monolayer and bilayer graphene field effect transistor using Verilog-A
Get PDFMonolayer and bilayer graphene field effect transistor modeling is presented in this paper. The transport model incorporated, works well for both drift diffusive and ballistic conditions. The validity of the model was checked for various device dimensions and bias voltages. Performance parameters affecting operation of graphene field effect transistor in various region of operation are optimized. Model was developed to verify transfer characteristics for monolayer and bilayer graphene field effect transistor. Results obtained prove the ambipolar property in Graphene. MATLAB is used for numerical modeling for systematic performance evaluation of parameters in graphene. The tool used to simulate the characteristics is cadence Verilog-A which describe analog component structure
Recurrence relation and DNA sequence: A state-of-art technique for secret sharing
Get PDFDuring the transmission over the Internet, protection of data and information is an important issue. Efficient cryptographic techniques are used for protection but everything depends on the encryption key and robustness of encryption algorithm. Threshold cryptography provides the development of reliable and strong encryption and key management machine which can reconstruct the message even in the case of destruction of some particular numbers of shares and at the opposite the data cannot be reconstructed unless an allowable set of shares are been gathered. The earlier techniques available in literature result in high computational complexity in the course of both sharing and reconstructing of message. Our method employs a brand new easy protecting technique based totally on unit matrix. The simple AND operation is used for percentage generation and reconstruction can be finished by way of easy ORing the stocks with threshold cost. We are proposing a sharing approach in conjunction with conventional cryptography technique for key control to make the key greater sturdy and for encryption we have used a session key the use of the idea of recurrence relation and DNA series Different types of experimental results confirm authenticity, confidentiality, integrity and acceptance of our technique
SoC-FPGA systems for the acquisition and processing of electroencephalographic signals
Get PDFReal-time acquisition and processing of electroencephalographic signals have promising applications in the implementation of brain-computer interfaces. These devices allow the user to control a device without performing motor actions, and are usually made up of a biopotential acquisition stage and a personal computer (PC). This structure is very flexible and appropriate for research, but for final users it is necessary to migrate to an embedded system, eliminating the PC from the scheme. The strict real-time processing requirements of such systems justify the choice of a system on a chip field-programmable gate arrays (SoC-FPGA) for its implementation. This article proposes a platform for the acquisition and processing of electroencephalographic signals using this type of device, which combines the parallelism and speed capabilities of an FPGA with the simplicity of a general-purpose processor on a single chip. In this scheme, the FPGA is in charge of the real-time operation, acquiring and processing the signals, while the processor solves the high-level tasks, with the interconnection between processing elements solved by buses integrated into the chip. The proposed scheme was used to implement a brain-computer interface based on steady-state visual evoked potentials, which was used to command a speller. The first tests of the system show that a selection time of 5 seconds per command can be achieved. The time delay between the user’s selection and the system response has been estimated at 343 µs
Image processing using a reconfigurable platform: Pre-processing block hardware architecture
Get PDFReal time image processing is a challenging task in which fetching the sub image requires offset memory access apart from core processing needs. This paper aims at overcoming the offset needs for memory addressing in pre-processing blocks. Another feature of this present work is to appending the image data with customized algorithmic reequipments viz duplicating, zero padding. For KxK kernel size, the proposed hardware architecture can be programmed to fetch K pixels in one cycle, reducing the data access time. Results have been compared with software-based processing for KxK spatial filtering. performance indicates significant timing improvement using proposed pre-processing hardware block