International Journal of Reconfigurable and Embedded Systems (IJRES)
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454 research outputs found
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Digital brain: Model-based framework for dependable electroencephalogram sensing and actuation in internet of things system
Get PDFReal-time brain internet of thing (IoT) frameworks are expensive. But, creating a cheaper framework has been quickened incredibly by the superior investigation that's being done on virtual brain. The passing of an imperative individual on a mystery mission is considered delicate data and must be taken care of with as much security as conceivable. By guaranteeing this discreteness, the time taken for the message of their passing to reach the pertinent specialist is expanded to up to a few days. The time taken to provide the message is as well. These days, the advancements in equipment expanding the capacities of the virtual brain and of the wearable brain IoT sensors have made the advancement of various unused program systems conceivable for engineers to make valuable applications that combine the human brain with IoT. Different tactile pathways are too empowered for communications of the human brain with bigger measured data. The fundamental point of this extend is to transfer secret records onto the clouds safely
Systematising troubleshooting of disputes in network
Get PDFWith the growing network size, virtualization everywhere, it is getting more difficult to configure and manage the network devices. Software Defined Networking (SDN) is a way to address these problems. Application Centric Infrastructure (ACI) is the Cisco’s solution to SDN, with centralized automation and policy-driven application profiles. If there is any bug in the network or problem with the expected functionality of the network, ACI cases are opened in the Technical Assistance Centre (TAC) for troubleshooting the issue. Engineers currently troubleshoot ACI cases manually by using Command Line Interface (CLI) and trace for different events triggered by the policy pushes by logs generated at different stages of the ACI and from different servers responsible for this, which indeed is a very tedious, time consuming task and is prone to manual errors. This paper describes a way to automate the entire ACI troubleshooting process with the user-friendly GUI which can show the entire information needed for troubleshooting by extracting relevant information at every layer. By making use of FSM models the proposed solution can be extended to other areas which involve log analysis using CLI to extract relevant information and is not just limited to ACI
Characterization and hierarchical static timing analysis of mixed-signal design
Get PDFAs the technology grows, the tendency to increase the data rate also increases. Clocks with higher frequencies have to be generated to meet the increased data rate. Any mismatch between the clock rate and data rate will lead to the capture of the wrong data. Hence performing timing analysis for any design to validate the capture of correct data plays a major role in any System on chip. This paper explains the procedure followed to perform timing analysis for any mixed-signal design
FPGA based co-design of a speed fuzzy logic controller applied to an autonomous car
Get PDFThis paper invests in FPGA technology to control the speed of an autonomous car using fuzzy logic. For that purpose, we propose a co-design based on a novel fuzzy controller IP. It was developed using the hardware language VHDL and driven by the Zynq processor through an SDK software design written in C. The proposed IP acts according to the ambient temperature and the presence or absence of an obstacle and its distance from the car. The partitioning of the co-design tasks divides them into hardware and software parts. The simulation results of the fuzzy IP and those of the complete co-design implementation on a Xilinx Zynq board showed the effectiveness of the proposed controller to meet the target constraints and generate suitable PWM signals. The proposed hardware architecture based on 6-LUT blocks uses 11 times fewer logic resources than other previous similar designs. Also, it can be easily updated when new constraints on the system are to be considered, which makes it suitable for many related applications. Fuzzy computing was accelerated thanks to the use of digital signal processing blocks that ensure parallel processing. Indeed, a complete execution cycle takes only 7 us
Design and implementation of CNTFET based ternary 1x1 memories
Get PDFIn this paper presented Design and implementation of CNTFET based Ternary 1x1 RAM memories high-performance digital circuits. CNTFET Ternary 1x1 SRAM memories is implement using 32nm technology process. The CNTFET decresase the diameter and performance matrics like delay,power and power delay, The CNTFET Ternary 6T SRAM cell consists of two cross coupled Ternary inverters one is READ and another WRITE operations of the Ternary 6T SRAM cell are performed with the Tritline using HSPICE and Tanner tools in this tool is performed high accuracy. The novel based work can be used for Low Power Application and Access time is less of compared to the conventional CMOS Technology. The CNTFET Ternary 6T SRAM array module (1X1) in 32nm technology consumes only 0.412mW power and data access time is about 5.23ns
Processor performance metrics analysis and implementation for MIPS using an open source OS
Get PDFProcessor efficiency is a important in embedded system. The efficiency of the processor depends on the L1 cache and translation lookaside buffer (TLB). It is required to understand the L1 cache and TLB performances during varied load for the execution on the processor and hence studies the performance of the varying load and its performance with caches with MIPS and operating system (OS) are studied in this paper. The proposed methods of implementation in the paper considers the counting of the instruction execution for respective cache and TLB management and the events are measured using a dedicated counters in software. The software counters are used as there are limitation to hardware counters in the MIPS32. Twentyseven metrics are considered for analysis and proper identification and implemented for the performance measurement of L1 cache and TLB on the MIPS32 processor. The generated data helps in future research in compiler tuning, memory management design for OS, analyzing architectural issues, system benchmarking, scalability, address space analysis, studies of bus communication among processor and its workload sharing characterization and kernel profiling
Heuristic algorithms for dynamic scheduling of moldable tasks in multicore embedded systems
Get PDFDynamic scheduling of parallel tasks is one of the efficient techniques to achieve high performance in multicore systems. Most existing algorithms for dynamic task scheduling assume that a task runs on one of the multiple cores or a fixed number of cores. Existing researches on dynamic task scheduling methods have evaluated their methods in different experimental environments and models. In this paper, the dynamic task scheduling methods are systematically rearranged and evaluated
Smart helmet using internet of things
Get PDFThe rate of death relative to the size of the world’s population has remained constant, according to the world health organization (WHO). WHO targets to minimize the ratio of road death to the half by 2022. This paper discusses a way for accident detection and notification which can decrease this ratio. Piezoelectric sensors used inside a helmet to detect degree of trauma which interpret into electrical signal that used to determine if trauma is serious or not based on predetermined threshold. This trauma can be occuard due to any kind of accidents. So, this paper established a detection system to request instant help from emergency department and relatives by delivering them an SMS contains the latitude and longitude. In usual mode helmet can operate as tracking tool monitored by the relatives
512 bit-SHA3 design approach and implementation on field programmable gate arrays
Get PDFIn this work, the authors consider the newly selected Hash Secure (SHA-3) algorithm on FPGA Gateway. The design is logically optimized for zone efficiency by combining the Rho steps and the one-pass algorithm. Logically recording these three steps registers leads to usage 16% of the logical resources for all implementations. This in turn reduces the latency and increases the maximum operating frequency of the project. It uses only 240 sections and has a frequency of 301.02 MHz compared to the design results with the previous FPGA implementation described in SHA3-512, the design shows the Throughput-Per-Slice (TPS) ratio of 30, 1
Space-time trellis codes: Field programmable gate array approach
Get PDFThis paper presents an implementation of Space-time Trellis Codes for 4-state on FPGA. To reach the very high data rates provided in STTC, a lot of expensive high-speed Digital Signal Processors (DSPs) should be employed for the real time applications, while it might not be affordable. This fact has motivated in designing dedicated hardware implementations using Field Programmable Gate Array (FPGA) with low cost and power consumption. The hardware device XC3S400, family Xilinx Spartan-3, and package PQ208 are used in this project, in which the STTC encoder and decoder utilizes maximum 10% and 22% as that of available device capacity respectively. The design has been simulated and synthesized successfully in Xilinx integrated software environment