3,356 research outputs found
Design and Validation of Network-on-Chip Architectures for the Next Generation of Multi-synchronous, Reliable, and Reconfigurable Embedded Systems
No full textNETWORK-ON-CHIP (NoC) design is today at a crossroad. On one hand, the
design principles to efficiently implement interconnection networks in the
resource-constrained on-chip setting have stabilized. On the other hand,
the requirements on embedded system design are far from stabilizing. Embedded
systems are composed by assembling together heterogeneous components featuring
differentiated operating speeds and ad-hoc counter measures must be adopted
to bridge frequency domains. Moreover, an unmistakable trend toward enhanced
reconfigurability is clearly underway due to the increasing complexity of applications.
At the same time, the technology effect is manyfold since it provides unprecedented
levels of system integration but it also brings new severe constraints
to the forefront: power budget restrictions, overheating concerns, circuit delay and
power variability, permanent fault, increased probability of transient faults.
Supporting different degrees of reconfigurability and flexibility in the parallel
hardware platform cannot be however achieved with the incremental evolution of
current design techniques, but requires a disruptive approach and a major increase
in complexity. In addition, new reliability challenges cannot be solved by using
traditional fault tolerance techniques alone but the reliability approach must be
also part of the overall reconfiguration methodology.
In this thesis we take on the challenge of engineering a NoC architectures for
the next generation systems and we provide design methods able to overcome the
conventional way of implementing multi-synchronous, reliable and reconfigurable
NoC. Our analysis is not only limited to research novel approaches to the specific
challenges of the NoC architecture but we also co-design the solutions in a single
integrated framework. Interdependencies between different NoC features are
detected ahead of time and we finally avoid the engineering of highly optimized solutions
to specific problems that however coexist inefficiently together in the final
NoC architecture. To conclude, a silicon implementation by means of a testchip
tape-out and a prototype on a FPGA board validate the feasibility and effectivenes
Optimizing built-in pseudo-random self-testing for network-on-chip switches
No full textMost BIST architectures use pseudo-random test pattern generators. However, whenever this technique has been applied to on-chip interconnection networks, overly large testing latencies have been reported. On the other hand, alternative approaches either suffer from large area penalties (like scan-based testing or the use of deterministic test patterns) or poor coverage of faults in the control path (functional testing). This paper presents the optimization of a built-in self-testing framework based on pseudo-random test patterns to the microarchitecture of network-on-chip switches. As a result, fault coverage and testing latency approach those achievable with deterministic test patterns while materializing relevant area savings and enhanced flexibility
A imagem de Alessandro Baricco no Brasil
No full textDissertação (mestrado) - Universidade Federal de Santa Catarina, Centro de Comunicação e Expressão, Programa de Pós-Graduação em Estudos da Tradução, Florianópolis, 2013.Com a intenção de delinear o modo pelo qual o escritor italiano Alessandro Baricco se inseriu no sistema literário brasileiro e os caminhos percorridos pelos seus livros traduzidos, esta dissertação dá voz às experiências tradutórias de seus tradutores. A inserção de Bariccono Brasil tem seu início em 1997, através de uma proposição da Profa. Dra. Roberta Barni à editora Iluminuras da tradução de Oceano Mare. A partir daí, outras sete obras foram publicadas no Brasil, sendo três delas traduzidas por Roberta Barni e as outras quatro por quatro tradutores diferentes. De um lado, considera-se o tradutor como figura principal namediação entre culturas, e, de outro, se analisa a realidade desta figuradentro do sistema literário, sua invisibilidade, seus limites e o exercíciode sua profissão. A pesquisa conta, ainda, com críticas e resenhas referentes ao autor italiano publicadas em jornais consagrados no Brasil, considerando estas como parte constituinte da imagem de Baricco refletida em território nacional. Abstract : Intending to delineate the way the Italian writer Alessandro Baricco has been inserted in the Brazilian literary system and the paths his translated books have followed, this thesis gives voice to the translating experiences of his translators. Baricco's insertion in Brazil began in 1997, through a personal project of Dr. Roberta Barni, with her translation of Oceano Mare. Since then, seven other of his works have been published in Brazil, three of which were translated by Roberta Barni and the other four by four different translators. On the one hand,the translator is considered as the main figure in mediation betweencultures and, on the other, this figure's reality is analyzed within theliterary system: its invisibility, its limits and its professional practice. Criticisms and reviews of this Italian author published in well established Brazilian newspapers are also considered, with the understanding that they are part of Baricco's image reflected here
Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches
No full textThis paper contributes to the maturity of the GALS NoC design practice by advocating for tight integration of GALS synchronization interfaces into NoC architecture building blocks. At the cost of re-engineering the input/output stages of NoC switches and network interfaces, this approach proves capable of materializing GALS NoCs with the same area and power of their synchronous counterparts, while reducing latency at the clock domain boundary. This design style is experimented in this paper with a mesochronous synchronizer and a dual-clock FIFO, which are tightly coupled with the switches of the xpipesLite NoC architecture
A library of dual-clock FIFOs for cost-effective and flexible MPSoC design
No full textCustomization of IP blocks in a multi-processor system-on-chip (MPSoC) is the historical approach to the cost-effective implementation of such systems. A recent trend consists of structuring a MPSoC into loosely coupled voltage and frequency islands to meet tight power budgets. In this context, synchronization between islands of synchronicity becomes a major design issue. Dual-clock FIFOs compare favorably with respect to synchronizer-based designs and pausible clocking interfaces from a performance viewpoint, but incur a significant area, power and latency overhead. This paper proposes a library of dual-clock FIFOs for cost-effective MPSoC design, where each architecture variant in the library has been designed to match well-defined operating conditions at the minimum implementation cost. Each FIFO synchronizer is suitable for plug-and-play insertion into the NoC architecture and selection depends on the performance requirements of the synchronization interface at hand. Above all, components of our synchronization library have not been conceived in isolation, but have been tightly co-designed with the switching fabric of the on-chip interconnection network, thus making a conscious use of power-hungry buffering resources and leading to affordable implementations in the resource constrained MPSoC domain
Cooperative Built-in Self-Testing and Self-Diagnosis of NoC Bisynchronous Channels
No full textThis paper proposes a built-in self-test/self-diagnosis procedure at start-up of an on-chip network (NoC) for bisynchronous communication channels. Concurrent BIST operations are carried out after reset at each switch, thus resulting in scalable test application time with network size. The key principle consists of exploiting the inherent structural redundancy of the NoC architecture in a cooperative way for the effective diagnosis and error detection. At-speed testing of stuck-at faults can be performed in less than 4000 cycles regardless of their size, with an hardware overhead of less than 30%. © 2012 IEEE
Technology-Aware Communication Architecture Design for Parallel Hardware Platforms
No full textThis chapter reviews techniques for technology-aware connectivity design for the early planning of NoC architectures. On one hand, it contrasts several connectivity patterns taking the perspective of their mapping efficiency onto the 2-D silicon surface, and characterizes to which extent the theoretical properties of a topology are offset by the physical implementation trade-offs. On the other hand, it reviews a few implementation variants of the globally asynchronous locally synchronous synchronization paradigm and reviews design techniques for cost-effective and robust implementation of synchronization interfaces. Overall, this chapter describes the key steps that designers have to take to change the appealing NoC concept into mature NoC technology
Process variation and layout mismatch tolerant design of source synchronous links for GALS networks-on-chip
No full textSynchronization interfaces in a network-on-chip
(NoC) are becoming vulnerable points that need to be safeguarded
against link delay variations and signal misalignments.
This paper addresses the challenge of designing a process
variation and layout mismatch tolerant link for GALS NoCs by
implementing a self-calibration mechanism. A variation detector
senses the variability-induced misalignment between data lines
with themselves and with the transmitter clock routed with
data in source synchronous links. Then, a suitable delayed
replica of the transmitter clock is selected for safe sampling
of misaligned data. The paper proves correct operation of the
GALS link augmented with the variation detector and compares
its reliability with that of a detector-less link, beyond proving
robustness with respect to the delay variability affecting the
detector itself
Power efficiency of switch architecture extensions for fault tolerant NoC design
No full textThe increasingly parallel landscape of embedded computing platforms is bringing the reliability concern for the on-chip interconnection network (NoC) to the forefront. While very few works in the open literature bring their error recovery mechanisms down to microarchitectural and physical implementation, this paper documents the effort of optimizing a baseline NoC switch architecture for different fault-tolerant strategies against single-event upsets. As key contributions achieved, we not only come up with a new efficient fault-tolerant flow control protocol, but also we contrast correction vs. retransmission oriented switch microarchitectures, each implementing both data and control path protection, with physical implementation awareness. The accuracy of the analysis methodology enables us to report counterintuitive power-reliability trade-offs between the design points, serving as guidelines for implementing fault-tolerant communication in a power-constrained environment
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