1,721,114 research outputs found
Francorum
No full textRiccio, Michele De regibus Hierosolymorum lib. I. VD16 R 2175Riccio, Michele De regibus Hispaniae lib. III. VD16 R 2177Riccio, Michele De regibus Neapolis et Siciliae lib. IV. VD16 R 2179Riccio, Michele De regibus Ungariae lib. II VD16 R 2181Bibliografischer Nachweis: VD16 R 2173Erscheinungsvermerk in Vorlageform im Kolophon: Basileae, Apvd Ioannem Frobenivm. Mense Ivlio. Anno M. D. XVII.Titelrahmen mit Druckermarke, Verlegermarke am End
De regibus Ungariae lib. II
No full textMit Druckermarke (letztes Blatt recto), Titelumrahmung u. ZierinitialenDrucker/Erscheinungsjahr nach Kolophon: "BASILEAE, APVD IOANNEM FROBENIVM. MENSE IVLIO. ANNO M. D. XVII.
Analysis on the Self-Sustained Oscillation of SiC MOSFET Body Diode
No full textUnder certain conditions, self-sustained oscillation may occur during reverse recovery transient of high-side silicon carbide (SiC) MOSFET body diode in the half-bridge circuit. In this article, two distinct positive feedback mechanisms that can excite the self-sustained oscillation are identified based on the double-pulse test. To investigate the instability of the two types of oscillation, a small signal ac model of the half-bridge circuit is proposed. With the model utilized, the parametric sensitivities of various parameters on the self-sustained oscillation are analyzed. The analyses reveal the oscillatory criteria, which provides effective guidelines to prevent the oscillation. In the end, the oscillation prevention guidelines are validated by the experiment. The experimental results demonstrate that the proposed theoretical treatment can provide reasonable guidelines to suppress the two types of self-sustained oscillation
A Scalable SPICE Electrothermal Compact Model for SiC MOSFETs: A Comparative Study between the LEVEL-3 and the BSIM
No full textIn this paper, two implementations of a SPICE-based compact model for SiC MOSFETs are presented. The two versions rely on widely adopted LEVEL-3 and BSIM 4.6.1 models, respectively. The paper discusses the feasibility of adopting these two models for the description of SiC power MOSFETs. Furthermore, after calibrating the DC characteristics on target experimental data coming from 1.7 kV-60 A MOSFETs, a comparison between the accuracy of the two is presented
Investigation on the Self-Sustained Oscillation of Superjunction MOSFET Intrinsic Diode
No full textThis paper presents the analyses on the self-sustained oscillation of superjunction MOSFET intrinsic diode. At first, the characteristics of the self-sustained oscillation for the superjunction MOSFET intrinsic diode are identified by the double-pulse switching test. The test results show that the self-sustained oscillation with significant self-amplification phenomenon can be triggered during the reverse recovery transient of superjunction MOSFET intrinsic diode. Based on the Sentaurus TCAD simulation, the self-sustained oscillation is reproduced. The simulation results reveal the root cause of the self-sustained oscillation. Due to the snappy reverse recovery of superjunction MOSFET intrinsic diode, the steep slope of diode snap off current can generate high voltage across the common source inductance, which drives the gate-source voltage and turns on the high-side MOSFET. The unexpected MOSFET turn-on can, in return, enhance the steepness of the current slope when the diode snap off. This leads to a positive feedback process and self-sustained oscillation is generated. In the end, based on the theoretical analyses and experimental results, the necessary methods that can suppress the oscillation are presented
Thermal-aware design and fault analysis of a DC/DC parallel resonant converter
No full textIn this paper a 3-D electrothermal (ET) analysis of a DC-DC parallel resonant converter (PRC) for constant current (CC) application is presented. A full 3-D ET simulation approach is proposed at application level to provide a support for the design stage and to analyse possible fault conditions inside the active devices. Simulations and measurements have been performed on a 100 W-2 A prototype of a PRC-CC circuit with 80 kHz nominal switching frequency.
In particular, in the reported case study, the analysis has been focused on the full-bridge section of the circuit in order to prove the effect of the soft switching operation, introduced by the resonant technique, and consider the effect of possible fault conditions. To this purpose an unexpected short-circuit condition on a power MOSFET composing the H-bridge is considered, to evaluate the ET circuit behaviour and the time-to-failure of the power section. Considerations are carried out in terms of minimum requirements of protection circuits which must be fulfilled in order to avoid catastrophic system failure.
A second power converter, rated for 1.5 kW, has been then designed, based on the same circuital topology, and an ET simulation has been performed in order to carry out considerations on the effect of mismatches among the input bridge devices. (C) 2014 Elsevier Ltd. All rights reserved
On the avalanche ruggedness of optimized termination structure for 600 v punch-through IGBTs
No full textIn this paper, the current paths in avalanche conditions of a Floating Field Ring (FFR) termination for a Punch-Through (PT) Insulated Gate Bipolar Transistor (IGBT) are analyzed. The design of the termination region is achieved with two different optimization techniques, and both static and dynamic electrical behavior are analyzed by means of 2D TCAD simulations, up to high current density levels. A comprehensive analysis of the Unclamped Inductive Switching (UIS) operation of the proposed terminations is carried-out with electro-thermal simulations. Although the behavior of both structures at low current levels is different, results show the same current crowding effect at the main junction for high current levels, resulting in a reduced conduction area of the overall termination, hence, of the avalanche reliability. Finally, experimental confirmation of filamentary current conduction during UIS test are detected on 600 V commercial devices by means of transient infrared thermography. © 2016 Elsevier Ltd. All rights reserved
Experimental analysis of electro-thermal instability in SiC Power MOSFETs
No full textIn this paper we experimentally demonstrate that SiC high voltage Power MOSFTEs exhibit an unstable electro-thermal behavior for given electrical conditions, depending on the chip thermal impedance. This instability can lead to hot-spot formation and eventually thermal runaway whit subsequent device destruction after a stressful short-circuit. The analysis was carried out on a commercial 1.2 kV SiC Power MOSFET by investigating the device electro-thermal behavior in short-circuit operation with a state-of-art IR thermographic set-up. By biasing the device at different gate voltages, the stable and unstable regions are evidenced with electrical and thermal measurements. Finally an unstable behavior is triggered and an hot-spot coherent with the failure location is demonstrate
Experimental Detection and Numerical Validation of Different Failure Mechanisms in IGBTs During Unclamped Inductive Switching
No full textThe physics of the different failure modes that limit the maximum avalanche capability during unclamped inductive switching (UIS) in punchthrough (PT) and not PT (NPT) insulated-gate bipolar transistor (IGBT) structures is analyzed in this paper. Both 3-D electrothermal numerical simulations and experimental evaluations support the theoretical analysis. Experimental results for UIS test show that, at low time duration (or inductance value) of the test, the UIS limit moves from energy limitation to current limitation. While the energy limitation is well known, the current-limited failures are less studied. In this paper, the current limit for UIS test is analyzed in detail, and the cause is attributed to a filamentary current conduction due to the presence of a negative differential resistance (NDR) region in the – curve in breakdown. The filamentary current conduction locally increases the current density causing early device latch-up and possible device failure at a current much lower than the one dictated by energy limitations. The physical parameters that affect both the onset of NDR region and the failure current are discussed for both an NPT trench IGBT structure with a local lifetime control and a PT trench IGBT structure with a field-stop layer
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