1,721,102 research outputs found
Error detection and correction in content addressable memories by using bloom filters
No full textA content addressable memory (CAM) is an SRAM-based memory that can be accessed in parallel to search for a given search word, providing as a result the address of the matching data. Like conventional memories, a CAM can be affected by the occurrence of single event upsets (SEUs) that can alter the content of one of more memory cells causing different effects such as pseudo-HIT or pseudo-MISS events. It is well known that, because of the parallel search performed by a CAM during the query of a word, a standard error correction code could not defend it against SEU events. In this paper, we propose a method that does not require any modification to a CAM's internal structure and, therefore, can be easily applied at system level. Error detection is performed by using a probabilistic structure called 'Bloom filter, which can signal if a given data is present in the CAM. Bloom filters permit to efficiently store and query the presence of data in a set. But, while a CAM suffers from SEU induced errors, the probabilistic nature of Bloom filters has as a consequence the so called false-positive effect. This paper shows that, by combining the use of a Bloom filter with a CAM, the complementary limitations of these modules can be compensated. The combined use of a CAM and a Bloom filter is analyzed in different cases, showing that the proposed technique can be implemented with a low penalty in terms of area and power consumption.</p
An Experimental Comparison of RISC-V Processors: Performance, Power, Area and Security - Special Session Paper
Full text linkThe RISC-V instruction set architecture (ISA) has garnered significant interest from both industry and academia because of its open source nature. Recent years have witnessed a surge in published implementations of the RISC-V ISA, with various companies actively pursuing its adoption in their products. However, a comprehensive analysis comparing these emerging RISC-V processors with each other and against established embedded computing platforms has not yet been published. This paper presents an experimental evaluation of three high-performance RISC-V processors: BOOM, NOEL-V, and CVA6 (formerly Ariane). The investigation is conducted on a Xilinx Kintex-7 Field-Programmable Gate Array (FPGA) platform. We perform a detailed analysis of critical performance metrics, covering area footprint, power consumption, and performance efficiency. Additionally, we assess the security posture of these cores against transient execution attacks, a prominent contemporary security threat. Finally, a comparative evaluation is undertaken between the RISC-V processors and two conventional application-level ARM processors to elucidate technological discrepancies and application suitability. This analysis aims to provide valuable insights into the current state and potential of RISC-V processors within the embedded computing domain
Racetrack logic
Full text linkA building block for computing in memory systems is introduced. Based on the previously introduced racetrack memory proposed by IBM, a racetrack memory is used not only to store data but also to perform bitwise majority-based computations by coupling the memory with inputs provided by controllable magnets. This solution is defined as racetrack logic. Micromagnetic simulations are used to confirm that the proposed solution is technically viable
Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses
No full textHardware Trojan Horses (HTHs) are today a serious issue for both academy and industry because of their dramatic complexity and dangerousness. Indeed, it has been shown that HTHs may be effectively inserted in modern microprocessors allowing the attacker to run malicious software, to acquire root privileges and to steal secret information. We aim at reducing the dangerousness of information stealing HTHs by introducing a hardware security module in the microprocessor under protection. In particular, the proposed module is in charge of interacting with the execution flow in order to introduce software obfuscation during programs execution at runtime. The goal of such obfuscation is to minimize the probability of exposing sensitive information to the HTH by encrypting/decrypting it, by spreading it through microprocessor's registers and by submerging it among garbage data. We implemented a prototype of the proposed hardware security module and we proved its effectiveness and efficiency (in terms of area occupation and working frequency reduction) by integrating it into the RSD 32bit speculative, superscalar and out-of-order RISC-V microprocessor running a set of benchmark programs1,.</p
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Wireless Power Transmission for lunar applications
Full text linkWireless Power Transmission (WPT) is a viable technique to ensure continuous energy supply on the lunar surface, independent of lunar night cycles and location. A constellation of satellites orbiting the Moon, with the goal of collecting solar energy through their own solar panels and transmitting it to the surface via laser beam, allows for energy potentially anywhere on the lunar surface and surviving the lunar night in both energy and thermal terms. This paper analyzes the possible orbits of satellites to provide power for the most part of the lunar surface, starting with the lunar South Pole, which currently presents itself as the most interesting area for upcoming missions and future lunar bases. In addition, the requirements and possible solutions for the satellite navigation system around the Moon and the laser beam pointing system are discussed
Design and analysis of single-event tolerant slave latches for enhanced scan delay testing
No full textThe last few years have seen the development and fabrication of nanoscale circuits at high density and low power. Following a single-event upset (SEU), so-called soft errors due to internal and externally induced phenomena (such as -particles and cosmic rays in adverse environments) have been reported during system operation; this is especially deleterious for storage elements such as flip-flops. To reduce the impact of a soft error on flip-flops, hardening techniques have been utilized. This paper proposes two new slave latches for improving the SEU tolerance of a flip-flop in scan delay testing. The two proposed slave latches utilize additional circuitry to increase the critical charge of the flip-flop compared to designs found in the technical literature. When used in a flip-flop, the first (second) latch design achieves a 5.6 (2.4) times larger critical charge with 11% (4%) delay and 16% (9%) power consumption overhead at 32-nm feature size, as compared with the best design found in the technical literature. Moreover, it is shown that the proposed slave latches have also superior performance in the presence of a single event with a multiple-node upset.</p
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