65 research outputs found
Talitha cumi
No full textTitle from PDF caption (viewed on May 24, 2018).This archived document is maintained by the State Library of Oregon as part of the Oregon Documents Depository Program. It is for informational purposes and may not be suitable for legal purposes.Mode of access: Internet from the Oregon Government Publications Collection.Text in English
Study of the source and drain series resistance in SOI FinFETs triple gate transistors and with strained channel.
No full textEste trabalho apresenta o estudo do comportamento da resistência série de fonte e dreno em transistores SOI FinFET de porta tripla e com canal tensionado. Nos dispositivos SOI FinFETs há um aumento da resistência série de fonte e dreno devido ao estreitamento dessas regiões, sendo esse parâmetro considerado como uma das limitações quanto à introdução desses dispositivos em tecnologias futuras. O uso de tensão mecânica no canal dos dispositivos surge como alternativa para aumentar a condução de corrente através do aumento da mobilidade dos portadores do canal, reduzindo assim, a resistência total dos transistores e, conseqüentemente, a resistência série de fonte e dreno. Inicialmente, foi feito o estudo de alguns métodos de extração da resistência série de fonte e dreno existentes na literatura, com o objetivo de se obter o mais adequado para aplicação e análise posterior. Esse trabalho foi realizado baseado em resultados experimentais e em simulações numéricas que possibilitaram o entendimento físico do fenômeno estudado. A resistência série de fonte e dreno foi explorada em diferentes tecnologias, como transistores SOI FinFETs de porta tripla convencionais e sob influência de tensionamento uniaxial e biaxial. O uso do crescimento seletivo epitaxial (SEG) nas regiões de fonte e dreno altamente dopadas das diferentes tecnologias também foi analisado, pois com essa técnica, a resistência série de fonte e dreno é reduzida substancialmente não comprometendo a condução de corrente e a transcondutância. Os resultados obtidos das diferentes tecnologias com e sem o uso de SEG foram analisados e comparados mostrando que em transistores SOI FinFETs de porta tripla, com crescimento seletivo epitaxial, apresentam o menor valor da resistência série de fonte e dreno mesmo para aqueles sem tensão mecânica na região do canal.This work presents the study of the source and drain series resistance behavior in standard and strained SOI FinFETs triple gate transistors. In SOI FinFETs transistors there is an increase of the source and drain series resistance due to the narrow of these regions, being this parameter a key limiting factor to the next generations. The use of strained transistors is one of the potential technologies to the next generation high performance because it increase the drive current through an enhance in the carrier mobility, decreasing the transistors total resistance and, therefore, the source and drain series resistance. Initially, a study of some series resistance extraction methods, present in the literature was done, in order to obtain the most appropriate for applications and analysis subsequent. This work was done based on experimental results and numerical simulations, enabling the physical understanding of the phenomenon studied. The series resistance was explored in different technologies, as standard SOI FinFETs triple gates and with uniaxial and biaxial strain. The use of selective epitaxial growth (SEG) in the source and drain regions, with high doping levels, was also studied in the different technologies, because with the use of this technique, the series resistance decreases substantially without compromising the drive current and transconductance. The obtained results from the different technologies with and without the use of SEG were analyzed and compared showing that, SOI FinFETs triple gate transistors with SEG present the lower values of series resistance even for standard devices if compared with strained ones without the use of SEG
Study of the extensionless UTBOX SOI transistors as memory cell.
No full textO objetivo principal deste trabalho é o estudo de transistores UTBOX SOI não auto-alinhados operando como célula de memória de apenas um transistor aproveitando-se do efeito de corpo flutuante (1T-FBRAM single Transistor Floating Body Random Access Memory). A caracterização elétrica dos dispositivos se deu a partir de medidas experimentais estáticas e dinâmicas e ainda, simulações numéricas bidimensionais foram implementadas para confirmar os resultados obtidos. Diferentes métodos de escrita e leitura do dado 1 que também são chamados de métodos de programação do dado 1 são encontrados na literatura, mas com intuito de se melhorar os parâmetros dinâmicos das memórias como o tempo de retenção e a margem de sensibilidade e ainda, permitir um maior escalamento dos dispositivos totalmente depletados, o método de programação utilizado neste trabalho será o BJT (Bipolar Junction Transistor). Uma das maiores preocupações para a aplicação de células 1T-DRAMs nas gerações tecnológicas futuras é o tempo de retenção que diminui juntamente com a redução do comprimento de canal do transistor. Com o intuito de solucionar este problema ou ao menos retardá-lo, é apresentando pela primeira vez um estudo sobre a dependência do tempo de retenção e da margem de sensibilidade em função do comprimento de canal, onde se observou que esses parâmetros dinâmicos podem ser otimizados através da polarização do substrato e mantidos constantes para comprimentos de canal maiores que 50 no caso dos dispositivos não auto-alinhados e 80 nos dispositivos de referência. Entretanto, observou-se também que existe um comprimento de canal mínimo que é dependente do tipo de junção (30 no caso dos dispositivos não auto-alinhados e 50 nos dispositivos de referência) de modo que para comprimentos de canal abaixo desses valores críticos não há mais espaço para otimização dos parâmetros, degradando assim o desempenho da célula de memória. O mecanismo de degradação dos parâmetros dinâmicos de memória foi identificado e atribuído à amplificação da corrente de GIDL (Gate Induced Drain Leakage) pelo transistor bipolar parasitário de base estreita durante a leitura e o tempo de repouso do dado 0. A presença desse efeito foi confirmada através de simulações numéricas bidimensionais dos transistores quando uma alta taxa de geração de portadores surgiu bem próxima das junções de fonte e dreno somente quando o modelo de tunelamento banda-a-banda (bbt.kane) foi considerado. Comparando o comportamento dos dispositivos não auto-alinhados com os dispositivos de referência tanto nos principais parâmetros elétricos (tensão de limiar, inclinação de sublimiar, ganho intrínseco de tensão) como em aplicações de memória (tempo de retenção, margem de sensibilidade, janela de leitura), constatou-se que a estrutura não auto-alinhada apresenta melhor desempenho, uma vez que alcança maior velocidade de chaveamento devido a menor inclinação de sublimiar; menor influência das linhas de campo elétrico nas cargas do canal, menor variação da tensão de limiar, até mesmo com a variação da temperatura. Além disso, constatou-se que os dispositivos não auto-alinhados são mais escaláveis do que os dispositivos de referência, pois são menos susceptíveis à corrente de GIDL, apresentando menor campo elétrico e taxa de geração próximos das junções de fonte e dreno que os dispositivos de referência, alcançando então um tempo de retenção de aproximadamente 6 e margem de sensibilidade de aproximadamente 71 A/m. Segundo as especificações da International Technology Roadmap for Semicondutor de 2011, o valor do tempo de retenção para as memórias DRAM convencionais existentes no mercado de semicondutores é de aproximadamente 64. Com o intuito de aumentar o tempo de retenção das 1T-DRAMs a valores próximos à 64 recomenda-se então o uso da tecnologia não auto-alinhada e também a substituição do silício por materiais com maior banda proibida (band-gap), como exemplo o arseneto de gálio e o silício-carbono, dificultando assim o tunelamento dos elétrons e, consequentemente, diminuindo o GIDL.The main topic of this work is the study of extensionless UTBOX SOI transistors, also called underlapped devices, applied as a single transistor floating body RAM (1T-FBRAM single transistor floating body access memory). The electrical characterization of the devices was performed through static and dynamic experimental data and two dimensional simulations were implemented to confirm the obtained results. In the literature, different methods to write and read the data 1 can be found but in order to improve the dynamic parameters of the memories, as retention time and sense margin and still allows the scaling of fully depleted devices, the BJT (Bipolar Junction Transistor) method is used in this work. One of the biggest issues to meet the specifications for future generations of 1T-DRAM cells is the retention time that scales together with the channel length. In order to overcome this issue or at least slow it down, in this work, we present for the first time, a study about the retention time and sense margin dependence of the channel length where it was possible to observe that these dynamic parameters can be optimized through the back gate bias and kept constant for channel lengths higher than 50 nm for extensionless devices and 80 nm for standard ones. However, it was also observed that there is a minimal channel length which depends of the source/drain junctions, i.e. 30 nm for extensionless and 50 nm for standard devices in the sense that for shorter channel lengths than these ones, there is no room for optimization degrading the performance of the memory cell. The mechanism behind the dynamic parameters degradation was identified and attributed to the GIDL current amplification by the lateral bipolar transistor with narrow base. Simulations confirmed this effect where higher generation rates near the junctions were presented only when the band-toband- tunneling adjustment was considered (bbt.kane model). Comparing the performance of standard and extensionless devices in both digital and analog electrical parameters and also in memory applications, it was found that extensionless devices present better performance since they reach faster switching which means lower subthreshold slope; less influence of the electrical field in the channel charges; less variation of the threshold voltage even increasing the temperature. Furthermore, it was seen that the gate length can be further scaled using underlap junctions since these devices are less susceptible to the GIDL current, presenting less electric field and generation rate near the source/drain junctions and reach a retention time of around 4 ms and sense margin of 71A/m. According to the International Technology Roadmap for Semiconductor of 2011, the retention time for the existing DRAM is around 64 ms. In order to increase the retention time of the 1T-DRAMs to values close to 64 ms it is recommended the use of extensionless devices and also the substitution of silicon by materials with higher band gap, i.e., gallium arsenide and siliconcarbon, which makes difficult the electron tunneling therefore, decreasing the GIDL
Link dancer hits the main stage [Article]
No full textThe Theatre and Dance Platform holds a digital copy (PDF) of the archived newsletter in the Lucy Guerin Inc collection.Article on WAAPA graduate dancer Talitha Maslin, who performed in the premiere season of Lucy Guern's Human Interest Story, Merlyn Theatre, Southbank, VIC, 23 July 2010. Author unknown
The Pentaport: Designing a safe gateway for complex endovascular aortic repair
No full text“A ruptured AAA [Abdominal Aortic Aneurysm] is the 15th leading cause of death in the country, and the 10th leading cause of death in men older than 55” in the United States, states Singh (n.d.), in the Society for Vascular Surgeons. Such Abdominal Aortic Aneurysms (AAA, see Figure 2.2) are increasingly treated by endovascular surgery, during which stent grafts are placed in the ballooned vessel through access sites such as the femoral (thigh) arteries, a procedure called Endo Vascular Aneurysm Repair (EVAR). 10% of patients has an aneurysm near significant arteries (Mayo Clinic, 2019), called a complex AAA, requiring stent grafts fitted with fenestrations (FEVAR, see Figure 2.1) or side branches (BEVAR). After puncture of the femoral artery, an introducer sheath is placed in the vessel, functioning as a re-usable access point to the arterial system. The sheath prevents blood from flowing out of the artery and enables entrance of tools such as guide wires, catheters and smaller sheaths into the arteries. However, treatment of complex AAA requires introduction of multiple tools (up to 5) through the sheath simultaneously, compared to just one or two during EVAR. With every additional tool being introduced, the valve’s capability of adequate closure is reduced even more. This results in leakage that can lead to significant blood loss for the patient. The Pentaport is a new, safe gateway for complex endovascular aortic repair (Figure 2.3). It functions as an add-on for commonly used sheath models. A leakproof ‘plug & screw’ connection facilitates safe and easy fastening to large-bore introducer sheaths. The Pentaport minimises blood leakage. Preventing severe blood losses of 2L or even more during one surgery, spares a heavy attack on the patient’s condition and eliminates the need for costly consequences, such as cell-saving or blood transfusion. In addition, it prevents the need for lengthy recatheterisation efforts (up to 60 minutes) and possible harm to the patient’s arteries. The design was evaluated and proof of concept was achieved, through functionality tests in simulated environments and usability tests with medical specialists. Integrated Product Design | Medisig
TOLOK UKUR PELANGGARAN HAK INTEGRITAS BERDASARKAN PASAL 5 AYAT (1) HURUF E UNDANG-UNDANG NOMOR 28 TAHUN 2014 TENTANG HAK CIPTA TERHADAP KARYA FOTOGRAFI, LUKISAN DAN GAMBAR
No full textTalitha Nuroini Ahdianitasary, Afifah Kusumadara, S.H., LL.M., SJD., Moch. Zairul Alam, S.H., M.H. Fakultas Hukum Universitas Brawijaya [email protected] ABSTRAK Hak integritas di Indonesia diatur dalam Pasal 5 ayat (1) huruf e UU Nomor 28 Tahun 2014 Tentang Hak Cipta, yang memberikan hak kepada pencipta untuk “mempertahankan haknya dalam hal terjadi distorsi Ciptaan, mutilasi Ciptaan, modifikasi Ciptaan atau hal yang bersifat merugikan kehormatan diri atau reputasinyaâ€. Penerapan pasal tersebut dalam analisis kasus diperlukan tolok ukur terlebih dahulu. Tetapi hingga saat ini belum ada putusan pengadilan tentang pelanggaran hak integritas yang dapat menjadi acuan tolok ukur Pasal 5 ayat (1) huruf e. Secara tidak langsung, permasalahan ini berpengaruh pada banyaknya tindakan pengubahan atau perusakan ciptaan yang dilakukan dan disebarluaskan pada sosial media, khususnya karya fotografi, lukisan dan gambar. Pada penelitian yuridis normatif ini, penulis akan menganalisis teori-teori yang berkaitan dengan hak cipta dan hak integritas untuk mengetahui tolok ukur tersebut. Penulis juga membandingkan pengaturan hak integritas serta tolok ukur pelanggaran hak integritas di Indonesia dengan di negara-negara Uni-Eropa. Penelitian menggunakan pendekatan perundang-undangan, pendekatan perbandingan hukum dan pendekatan kasus. Kesimpulannya adalah bahwa tolok ukur pelanggaran hak integritas dititik beratkan pada kehormatan diri dan reputasi pencipta. Pembuktian adanya kerugian reputasi dapat dilihat dari kerugian pelaksanaan hak ekonomi atau penurunan pendapatan pencipta yang bersumber dari ciptaan yang diubah. Kemudian, hasil perbandingan menunjukkan bahwa pengaturan dan tolok ukur pelanggaran hak integrtas di negara-negara Uni-Eropa berbeda-beda, begitupun di Indonesia. Sehingga, tolok ukur yang berlaku di suatu negara tidak dapat diterapkan di negara lain. Kata Kunci: Hak Cipta, Tolok Ukur, Pelanggaran, Hak Integritas. ABSTRACT Moral rights are regulated in Article 5 Paragraph (1) letter e of Act Number 28 of 2014 concerning Copyright, enabling creators to keep their rights in case of creation distortion, creation mutilation, creation modification, or anything that can harm dignity or reputation of the creators. However, the implementation of the Article in regard to analysis of the cases requires scope or benchmark, and there has not been any court decision that regulates violation of moral rights for the reference of Article 5 Paragraph (1) letter e. Indirectly, this issue affects the incidence of modification or distortion of creation that may be made viral on social media, especially for photography, paintings, or images. This research is aimed to analyse theories related to copyright and moral rights to find out the scope. The author also made a comparison between moral rights and the extent of violation of moral rights in Indonesia and those in European Union. With statute, comparative, and case approaches, this research reveals that the violation of moral rights is emphasised on dignity and reputation of the creators, where both are reflected from the loss in economic implementation and falling profit gained by the creators stemming from modified creation. Moreover, the regulation and scope in terms of the violation of moral rights in European Union are varied, so is in Indonesia, meaning that the scope applying in a country is not applicable in another country. Keywords: Copyright, Scope, Violation, Moral Rights Â
An analysis of the U.S. Bureau of Prisons managerial/administrative support for its EEO program, 1981
No full textThe primary intent of this paper is to analyze managerial/administrative support for the Equal Employment Opportunity Program in the U.S. Bureau of Prisons. The analysis involves the examination of three problem areas in the Equal Employment Opportunity Program. The problem areas are identified as a lack of resources, a lack of personnel, and a lack of enthusiasm among employees for the program. The evaluation of these problem areas gives insight to the support obtained from management. Recommendations for improving these problem areas follow the analysis
Construction and Analysis of a Discrete Heat Equation Using Dynamic Consistency: The Meso-Scale Limit
No full textWe present and analyze a new derivation of the meso-level behavior of a discrete microscopic model of heat transfer. This construction is based on the principle of dynamic consistency. Our work reproduces and corrects, when needed, all the major previous expressions which provide modications to the standard heat PDE. However, unlike earlier efforts, we do not allow the microscopic level parameters to have zero limiting values. We also give insight into the difficulties of constructing physically valid heat equations within the framework of the general mathematically inequivalent of difference and differential equations
Talitha Espiritu’s Passionate Revolutions: The Media and the Rise and Fall of the Marcos Regime
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