1,731,516 research outputs found
A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories
Full text linkIn spite of the mature cell structure, the memory controller architecture of Multi-level cell (MLC) NAND Flash memories is evolving fast in an attempt to improve the uncorrected/miscorrected bit error rate (UBER) and to provide a more flexible usage model where the performance-reliability trade-off point can be adjusted at runtime. However, optimization techniques in the memory controller architecture cannot avoid a strict trade-off between UBER and read throughput. In this paper, we show that co-optimizing ECC architecture configuration in the memory controller with program algorithm selection at the technology layer, a more flexible memory sub-system arises, which is capable of unprecedented trade-offs points between performance and reliabilit
EDACs and test integration strategies for NAND flash memories
Full text linkMission-critical applications usually presents several critical issues: the required level of dependability of the whole mission always implies to address different and contrasting dimensions and to evaluate the tradeoffs among them. A mass-memory device is always needed in all mission-critical applications: NAND flash-memories could be used for this goal. Error Detection And Correction (EDAC) techniques are needed to improve dependability of flash-memory devices. However also testing strategies need to be explored in order to provide highly dependable systems. Integrating these two main aspects results in providing a fault-tolerant mass-memory device, but no systematic approach has so far been proposed to consider them as a whole. As a consequence a novel strategy integrating a particular code-based design environment with newly selected testing strategies is presented in this pape
PLA Design in NAND Structure
No full textA NAND (serial gating) structure PLA of the MOS poly-silicon gate process has been developed for high density and medium fast speed VLSI application. Dynamic clocking is used for minimum power dissipation and
elimination of the ratio problem associated with static NAND gate. Ion-implantation for memory cell programming and the elimination of contact in the memory area drastically reduces the cell size, and reliability is improved .
A simple but effective self-timed clocking scheme is employed for better operating margins against process variations; the overhead chip area for the
clock generation is sufficiently small. The advantages of allowing metal signal and power lines to cross the PLA memory area is discussed. Some measured data
from a 3.5μm NMOS Si-gate process with regard to gate height and transistor sizes are also described
ELECTRICAL CHARACTERIZATION, PHYSICS, MODELING AND RELIABILITY OF INNOVATIVE NON-VOLATILE MEMORIES
No full textEnclosed in this thesis work it can be found the results of a three years long research
activity performed during the XXIV-th cycle of the Ph.D. school in Engineering Science of
the Università degli Studi di Ferrara. The topic of this work is concerned about the
electrical characterization, physics, modeling and reliability of innovative non-volatile
memories, addressing most of the proposed alternative to the floating-gate based
memories which currently are facing a technology dead end. Throughout the chapters of
this thesis it will be provided a detailed characterization of the envisioned replacements for
the common NOR and NAND Flash technologies into the near future embedded and
MPSoCs (Multi Processing System on Chip) systems. In Chapter 1 it will be introduced the
non-volatile memory technology with direct reference on nowadays Flash mainstream,
providing indications and comments on why the system designers should be forced to
change the approach to new memory concepts. In Chapter 2 it will be presented one of the
most studied post-floating gate memory technology for MPSoCs: the Phase Change
Memory. The results of an extensive electrical characterization performed on these
devices led to important discoveries such as the kinematics of the erase operation and
potential reliability threats in memory operations. A modeling framework has been
developed to support the experimental results and to validate them on projected scaled
technology. In Chapter 3 an embedded memory for automotive environment will be shown:
the SimpleEE p-channel memory. The characterization of this memory proven the
technology robustness providing at the same time new insights on the erratic bits
phenomenon largely studied on NOR and NAND counterparts. Chapter 4 will show the
research studies performed on a memory device based on the Nano-MEMS concept. This
particular memory generation proves to be integrated in very harsh environment such as
military applications, geothermal and space avionics. A detailed study on the physical
principles underlying this memory will be presented. In Chapter 5 a successor of the
standard NAND Flash will be analyzed: the Charge Trapping NAND. This kind of memory
shares the same principles of the traditional floating gate technology except for the storage
medium which now has been substituted by a discrete nature storage (i.e. silicon nitride
traps). The conclusions and the results summary for each memory technology will be
provided in Chapter 6. Finally, on Appendix A it will be shown the results of a recently
started research activity on the high level reliability memory management exploiting the
results of the studies for Phase Change Memories
NAND Flash Memory Organization and Operations
No full textNAND flash memories are well known for their uncomplicated structure, low cost, and high capacity. Their typical characteristics include architecture, sequential reading, and high density. NAND flash memory is a non-volatile type of memory and has low power consumption. The erasing of NAND Flash memory is based on a block-wise base. Since cells in a ash chip will fail after a limited number of writes, limited write endurance is a key characteristic of flash memory. There are many noise causes such as read or program disturbs, retention process, charge leakage, trapping generation, etc. Preferably, all errors in the storage would be adjusted by the ECC algorithm. The conclusion of all mentioned parasitic factors creates a set of external and internal influences which affects variable behaviour of memory in time. To prepare a review of all the important factors that affect the reliability and life-cycle endurance of NAND flash memories and was our main motivation for this paper.NAND flash memories are well known for their uncomplicated structure, low cost, and high capacity. Their typical characteristics include architecture, sequential reading, and high density. NAND flash memory is a non-volatile type of memory and has low power consumption. The erasing of NAND Flash memory is based on a block-wise base. Since cells in a ash chip will fail after a limited number of writes, limited write endurance is a key characteristic of flash memory. There are many noise causes such as read or program disturbs, retention process, charge leakage, trapping generation, etc. Preferably, all errors in the storage would be adjusted by the ECC algorithm. The conclusion of all mentioned parasitic factors creates a set of external and internal influences which affects variable behaviour of memory in time. To prepare a review of all the important factors that affect the reliability and life-cycle endurance of NAND flash memories and was our main motivation for this paper
NAND flash memory technologies
No full textThis book discusses basic and advanced NAND flash memory technologies, including the principle of NAND flash, memory cell technologies, multi-bits cell technologies, scaling challenges of memory cell, reliability, and 3-dimensional cell as the future technology. Chapter 1 describes the background and early history of NAND flash. The basic device structures and operations are described in Chapter 2. Next, the author discusses the memory cell technologies focused on scaling in Chapter 3, and introduces the advanced operations for multi-level cells in Chapter 4. The physical limitations for scaling are examined in Chapter 5, and Chapter 6 describes the reliability of NAND flash memory. Chapter 7 examines 3-dimensional (3D) NAND flash memory cells and discusses the pros and cons in structure, process, operations, scalability, and performance. In Chapter 8, challenges of 3D NAND flash memory are dis ussed. Finally, in Chapter 9, the author summarizes and describes the prospect of technologies and market for the future NAND flash memory
Memorie Flash a NAND
Full text linkIn questa tesi verranno trattate le memorie Flash. Partendo da una breve introduzione all'argomento, si studierà prima il funzionamento a livello fisico del transistor, il suo inserimento in un'architettura a NAND e i metodi di accesso e scrittura del dati in tale contesto. Verranno poi discussi l'affidabilità ed i principali problemi della tecnologia, insieme alle possibili soluzioni ad essi. Per concludere, una panoramica delle principali applicazioni delle memorie Flash nei nostri giorniope
Reliability of NAND Flash Memories
No full textThe continuous demand for NAND flash memories with higher performance and storage capabilities pushes the manufactures towards the limits of present technologies and to explore new solutions, both from the physical and the architectural point of view.
The memory reliability represents one of the major antagonist towards this un-stoppable technological evolution, since the correct operations must be assured not only when a new product is presented, but they must be demonstrated for the entire life cycle. In particular, the minimum number of write operations and the ability of keeping unaltered the stored information for years and years must be guaranteed.
In this chapter the principal reliability mechanisms affecting the traditional floating-gate NAND flash memories will be addressed: the physical aspects caused by charge transport and trapping in thin insulator layers as well as the in-correct behaviors related to the array architecture. It will also shown as these ef-fects increase dramatically their impact when Multi Level Cells (MLC) are con-sidered. New emerging mechanisms, such as Gate-Induce Drain Leakage (GIDL), Random Telegraph Noise (RTN) and temperature instabilities will also be ad-dressed
Numerical simulation of RDF and RTN in 3D NAND
No full textLAUREA MAGISTRALELa legge di Moore fa sì che i produttori di semiconduttori, di chip di memoria e di logica, possano ridurre i costi dei prodotti e incrementare le prestazioni aumentando la densità di transistor. La memoria NAND flash è uno dei supporti di archiviazione di tipo non-volatile per computer, in cui la relazione tra bit line e word line assomiglia a una porta NAND (NOT-AND). Nella tecnologia flash NAND attuale la tendenza dominante è l'architettura 3D piuttosto che l'architettura 2D, la quale è in grado di aumentare la densità di memoria linearmente, aumentando il numero di strati della pila di chip NAND 3D.
Per utilizzare meglio la tecnologia NAND 3D è necessaria la comprensione delle sue proprietà fisiche. Poiché il processo della trasformazione NAND da planare a 3D richiede l'uso di polisilicio, devono essere studiati anche i suoi conseguenti problemi di affidabilità. Questa tesi si concentra sulla fluttuazione casuale del drogante (RDF) e sul rumore telegrafico casuale (RTN) attraverso una simulazione numerica su una cella NAND 3D con TCAD (Technology Computer Aided Design) e MATLAB.
Il capitolo 1 introduce le nozioni fondamentali di NAND, in particolare: la ragione e l'impatto della trasformazione NAND 3D, la classificazione della NAND assieme ai suoi vantaggi e svantaggi, l’ottimizzazione della sua densità di transistor, ecc.. Questo capitolo si conclude con la presentazione della struttura NAND 3D con il canale verticale a "maccheroni" utilizzato per la simulazione.
Il capitolo 2 si concentra sul problema dell'affidabilità di NAND 3D, in particolare sulla fluttuazione casuale del drogante e sul rumore telegrafico casuale, illustrando l'origine di RDF e RTN. Sono riportati i risultati di ricerche altrui, che forniscono un'idea generale di cosa può influenzare queste grandezze.
Il capitolo 3 spiega in dettaglio come è stata eseguita la simulazione. Viene illustrato il modello creato da TCAD e vengono elencati i parametri rilevanti. In
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questo capitolo vengono inoltre illustrate le procedure della simulazione e i metodi per ottenere una cella NAND grain-random, trap-random.
Il capitolo 4 mostra i valori numerici ottenuti dalla simulazione. Dopo l’elaborazione, sono stati riportati in grafici, dai quali possiamo osservare la media di VT, la deviazione standard di VT e la pendenza RTN, rilevabile dalla tendenza di variazione delle curve. Inoltre, sono state date alcune interpretazioni per spiegare i dati ottenuti.
Il capitolo 5 riassume l’intero lavoro e completa la presentazione dei risultati della simulazione, concludendo con una proposta di possibile futura attività di ricerca.Moore's Law drives semiconductor manufacturers of memory and logic chips to reduce product costs and improve performance by increasing transistor density. NAND flash memory is one of the electronic non-volatile computer memory storage mediums, in which the relationship between the bit line and the word lines resembles a NAND (NOT-AND) gate. In NAND Flash technology, the mainstream of the market now is 3D architecture rather than 2D flat architecture, which can increase the memory density linearly by increasing the number of 3D NAND chip stack layers.
To better take advantage of the 3D NAND technology, understanding of its physical properties is necessary. As the NAND transform from planar to 3D, the process requires the use of polysilicon, the consequent reliability issues need to be studied. This thesis is going to focus on the random dopant fluctuation (RDF) and random telegraph noise (RTN) by doing numerical simulation on a 3D NAND cell with TCAD (Technology Computer Aided Design) and MATLAB.
Chapter 1 introduces the fundamental knowledge of NAND, including: the reason and impact of the transformation of 3D NAND, the classification of NAND with their advantages and disadvantages, the way to improve its storage density, etc.. In the end of this chapter, the structure of the 3D NAND with vertical “macaroni” channel that we used for the simulation is presented.
Chapter 2 concentrates on the reliability issue of 3D NAND, specifically, random dopant fluctuation and random telegraph noise. It explains the origin of RDF and RTN. Results gotten from others’ previous researches are concluded to provide a general idea of what may affect the magnitude of RDF and RTN.
Chapter 3 explains in details how the simulation was carried on. The model created by TCAD is displayed and relevant parameters are listed. This chapter also shows the procedure of the simulation flow and the method to get a grain-random, trap-random NAND cell.
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Chapter 4 shows the numerical values we got from the simulation. After being processed, they are put in figures, so we can observe the mean of VT, standard deviation of VT and RTN slope dependence visually from the variation tendency of the curves. Some interpretations are given to explain the data.
Chapter 5 summarizes this work and concludes the results of the simulation. Proposal of the future work is mentioned at last
3D NAND memory as radiation monitor
No full textThis thesis explores the feasibility of using 3D NAND flash memory as space radiation monitor. Space radiation is composed by ionizing particles such as protons and ions, which can be harmful to electronics. Shielding and Error Correcting Code can be implemented to counteract these effects. Monitoringthe space radiation environment is necessary to better understand the space radiation environment and design shielding and ECC according to the exposed dose of a spacecraft during its mission. Following the trend of miniaturization, using 3D NAND flash technology will drive down the cost of a radiation monitor. This allows for space radiation monitors which can be used on small satellites such as a picosatellites.Aerospace Engineerin
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