1,721,184 research outputs found
TRUNCATED BINARY MULTIPLIERS WITH MINIMUM MEAN SQUARE ERROR: ANALYTICAL CHARACTERIZATION, CIRCUIT IMPLEMENTATION AND APPLICATIONS
No full textBidimensional lifetime control for high speed low-loss PiN rectifiers
No full textIn the paper a lifetime control technique able to control device carrier lifetime not only in the axial direction, but also in the longitudinal direction (two-dimensional (2-D) lifetime control), is analyzed. Static and dynamic losses of p-i-n diode using 2-D lifetime control are studied through mixed mode circuit-device simulations. It is shown that the 2-D technique gives a better tradeoff between static and dynamic behavior with respect to electron irradiation technique. The comparison with axial lifetime control shows that, notwithstanding similar performances achieved using the two techniques, 2-D lifetime control provides greater design flexibilit
Duration of the High Breakdown Voltage Phase in Deep Depletion SOI LDMOS
No full textMeasurement results on the duration of the hightransient-
breakdown phase for a silicon-on-insulator (SOI) laterally
diffusedmetal–oxide–semiconductor (LDMOS) are presented.
The results are important since they give experimental evidence
on the practical applicability of the deep-depletion (DD) design
technique, which is an innovative concept that has been recently
proposed for SOI power devices. Measurements have been conducted
on DD SOI LDMOS devices using a nondestructive test
circuit that applies a voltage pulse with a definite amplitude and
duration on the drain terminal. Measurement results show that
the DD effect provides a high breakdown voltage (BV) phase that,
as an example, lasts for 15 μs when the applied voltage is 150 V,
which is a 65% increase over the static BV, and T = 125 ◦C. The
sustained overvoltage and the duration of the high BV phase make
the DD effect exploitable for modern power switching circuits
Limits and application of the newly proposed deep-depletion SOI LDMOS
No full textThe behaviour of a deep depletion (DD) silicon on insulator (SOI) lateral MOS (LDMOS) is analysed. DD of the substrate for an SOI device has been recently proposed as an innovative technique to design power devices featuring a transient breakdown higher than the static breakdown. DD is a dynamic effect that allows the design of a whole new generation of SOI power devices. Eligible applications are power conditioning circuits in which the device sustains transient voltages higher than bus voltage such as the flyback converter and the resonant circuits. Numerical simulation methods are used to analyse the behaviour of the device together with the effect of temperature, substrate carrier generation time and applied reverse bias on the duration of the transient breakdown phase. The results show that the newly proposed DD SOI device, an SOI power LDMOS using P− substrate, exhibits a static breakdown voltage of 190 V and sustains transient overvoltages up to 280 V. Furthermore, mixed-mode simulation of a complete Class E resonant converter using the proposed DD SOI device is presented
Numerical evaluation of bidimensional lifetime control as design technique for PiN rectifiers
No full textNumerical analysis of performance improvement available using lifetime control techniques able to control device carrier lifetime not only in the axial direction, but also in the longitudinal direction (2D lifetime control) is presented. Mixed mode numerical simulations are used to evaluate static and dynamic behavior of power PiN diodes using 2D lifetime control. The analysis shows that 2D lifetime control gives a better trade-off between static and dynamic behavior with respect to electron irradiation technique. Guidelines for optimal design are given. In the paper it is shown that 2D lifetime control is a very flexible design technique, since there are many lifetime profiles with similar effects on diode performance
Study and experiments regarding adavanced local lifetime control techniques for the design of fast and low loss PiN diodes
No full textThe project is directed to the study and to the characterization of the most advanced lifetime control techniques and to the optimal use of such techniques for the design PiN diode. During the research activity, experimental lifetime measurements on silicon irradiated with either he ions or protons, using different process parameters such as ions dose and energy, will be carried out. Lifetime measurements will be performed by using a recently proposed test structure that will be optimized to perform accurate measurements at arbitrary injection level. The proposed measurement technique is able to extract lifetime profile inside the structure and allows a complete characterization of semiconductor recombination centers
DEEP DEPLETION SOI POWER DEVICES
No full textThe paper presents an innovative design concept for SOI lateral power devices that exploits the deep depletion of the substrate to dynamically increase the voltage rating ofSOI devices. Numerical simulations of the device and experimental results demonstrate that the proposed physical effect is a viable way to design a whole new class of lateral power devices
One dimensional model for the duration of the high breakdown phase in deep depletion power devices
No full textThe paper presents a one dimensional model of the duration of the increased breakdown voltage phase in Deep Depletion power devices. The model includes the effect of bulk generation and space charge generation and is verified against numerical simulations of a Si-BOX-Si structure. The model is compared with experimental results regarding the duration of the increased breakdown voltage phase in a power LDMOS in SOI technology. The results show that the interface states are probably the limiting factor for the duration of the increased breakdown voltage phase
Modeling the Duration of the High Breakdown Voltage Phase in Deep Depletion Power Devices
No full textThe paper presents a one dimensional model for the duration of
the increased breakdown voltage phase in Deep Depletion power devices. The
model includes the effect of bulk generation and space charge generation that
is verified against numerical simulations of a nSi-BOX-pSi structure. The fi-
nal result of the model, the duration of the high breakdown voltage phase as
a function of device characteristic and the applied voltage, is verified against
experimental results regarding the duration of the increased breakdown voltage
phase in a power LDMOS in SOI technology. The results show that the interface states are probably the limiting factor for the duration of the increased
breakdown voltage phase
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