51 research outputs found
Effects of On-State Snap-back Characteristics on the Current Sharing of Parallel RC-IGBTs
No full textReverse Conducting RC-IGBTs are in continuous development for a wide range of voltage classes targeting different power electronics applications. One of the main challenges faced in the design of RC-IGBTs is the on-state snap-back characteristics. Hence, different collector short design concepts have been investigated in order to reduce or eliminate this type of behavior. All previous investigations are based on the assumption that a negative differential resistance zone in the IV output characteristics could lead to failure events when devices are operated in parallel. Some devices might not turn-on during switching transients under real operational conditions leading to very high current densities in the conducting devices. In this paper, the effects of the snap-back characteristics on the switching behavior of parallel RC-IGBTs is presented with the aid of TCAD simulations of 1200V RC-IGBT models. Furthermore, the paper will provide analysis of the current mis-sharing at device and circuit levels.</p
3.3 kV 4H-SiC Trench Semi-Superjunction Schottky Diode With Improved ON-State Resistance
No full textThis study describes the design and optimization of a 3.3 kV silicon carbide (SiC) semi-superjunction (semi-SJ) Schottky barrier diode (SBD). The proposed structure features a 7 μ m deep trench filled with silicon dioxide (SiO2). Aluminum (Al+) sidewall implants are carried out, which help to form a charge balance region. The on-state improvement of the proposed semi-SJ structure is 16.2%, compared to a planar diode. This results in a specific on-state resistance ( RON,SP ) of 6.2 m Ω⋅ cm2 , which surpasses the unipolar limit. The article also addresses the issue of poor blocking voltage performance associated with conventional termination techniques. To mitigate this problem, novel termination designs, which incorporate double-zone junction termination extension (DJTE) and optimally placed rings, are proposed and verified through technology computer-aided design (TCAD) simulations. The most promising structure allows, for the first time, for both a wide implantation window and a high breakdown voltage, reaching 98.3% (4365 V) of the ideal active cell breakdown
Performance Evaluation and Expected Challenges of Silicon Carbide Power MOSFETs for High Voltage Applications
No full textThis paper presents an overview of the main technical requirements of high voltage Silicon Carbide MOSFETs rated above 3300V when compared to the well-established requirements of Silicon IGBTs and diodes. Combined with a performance evaluation of existing 3300 V SiC MOSFET prototypes from ROHM, the paper will discuss the benefits and challenges facing these devices for targeting mainstream and future topologies employed in high power applications such as those in grid systems, railway traction and industrial drives. The paper will also attempt to provide an outlook into potential development trends towards exploiting the full benefits of SiC MOSFETs.</jats:p
OPTIMIZATION AND ADVANTAGES OF THE BIMODE INSULATED GATE TRANSISTOR
No full textAbstract. The Bi-mode Insulated Gate Transistor BIGT is a single chip reverse conducting IGBT concept, which is foreseen to replace the standard IGBT / Diode two chip approach in many high power semiconductor applications. Therefore, it is important to understand in detail the design challenges and performance trade-offs faced when optimizing the BIGT for different application requirements. In this paper, we present the main conflicting design trade-offs for achieving the overall electrical and thermal performance targets. We will demonstrate experimentally how on one hand, the BIGT provides improved design features which overcome the restrictions of the current state of the art IGBT/diode concepts, while on the other hand, a new set of tailoring parameters arise for an optimum BIGT behavior
Out-of-SOA performance in 3.3 kV SiC MOSFETs: Comparison between planar and quasi-planar trench
No full textMultidimensional device structures can improve the typical performance trade-off of semiconductor power transistors. In this paper, the on-state, reverse, and short-circuit performance of a SiC quasi-planar trench MOSFET are compared to those of a classical planar device through advanced 3-D TCAD simulations
15th INTERNATIONAL SEMINAR ON POWER SEMICONDUCTORS
No full textA Singular Point Source MOS (S-MOS) cell concept suitable for power semiconductor MOS based
devices is presented. The S-MOS differs from a standard Planar or Trench MOS cell in the manner by
which the total channel width per device area is determined. The S-MOS cell channel width is defined
as the peripheral length of a line running approximately along the N++ source and P channel junction
which is situated on a single gated trench side-wall. The length of the line can be established from a
singular point source implant for forming the N++ source region which corresponds to the shape of the
N++/P junction. The total channel width will therefore depend on the total number of gated trench side-
walls per chip. Despite a relatively short channel width obtained on a single trench side-wall, narrow
mesa dimensions between adjacent trenches will provide an adequate number of cells for adjusting the
total channel width as required for a given device performance. The S-MOS can be realized by simple
manufacturing processes and presents an alternative approach for MOS cell layouts by decoupling
critical design parameters (e.g., channel width, trench dimension and NPN transistor area). This
flexibility can lead to lower overall losses, lower gate charge levels, improved switching robustness and
controllability for different MOS based devices
Characterization of helium implantation in silicon for the optimisation of static and dynamic behaviour of power diodes
No full textTCAD analysis of short-circuit oscillations in IGBTs
No full textInsulated-Gate Bipolar Transistors (IGBTs) exhibit a gate-voltage oscillation phenomenon during short-circuit, which can result in a gate-oxide breakdown. The oscillations have been investigated through device simulations and experimental investigations of a 3.3-kV IGBT. It has been found that the oscillations are more likely to occur at low DC-link voltages, high gate voltages and low temperatures due to a charge-storage effect at the surface of the IGBT. Based on this insight, the charge-storage effect can be explained with a reduction in carrier velocity due to the electric field shape rotation during short circuit
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