104 research outputs found
A Metaphorical Touch of Sai Paranjape’s ‘Sparsh’
No full textOn the basis of the real life incident of Ajay Mittal, the film has been able to break the stereotype image of the blind characters and by Naseeruddin Shah Sai has a trusted and malleable actor to realize and implement her vision successfully. The Hindi feature film ‘Sparsh’ (Touch) (1980) directed by Sai Paranjape stars Naseeruddin Shah and Shabana Azmi playing the characters of a visually impaired principal and a sighted teacher of a blind school where both of them fall in love. Though their complexes create a hindrance between their mutual relationships, they try to reconnect and renew through the ‘touch’ of love. The film remains most memorable for the subtle acting of its lead duo besides the tackling of the issue of relationships with the visually handicapped, exhibiting the emotional and perceptional division between the worlds of the ‘blind’ and the ‘sighted’, portrayed by the characters. The National Film Award for Best Hindi Feature Film went to ‘Sparsh’. ‘Sparsh’ won various awards. Naseruddin Shah won the National Award for Best Actor for his acting in this film. ‘Sparsh’ is about the existence and emotion of the Principal and the Children of a Blind School. Sparsh’ has upheld the emotion, sensation and feeling of touch upon which blind people trust in the absence of sight. ‘Sparsh’ directed by Sai Paranjape is one rare narrative love story which a large section of Film Critics does not think anyone has attempted in Hindi film. This exceptional narrative adds a soft emotional dimension to the entire influence of the film. The film has been presented in a realistic manner with less use of highly dramatic and mainstream methods of filmmaking. The viewers therefore can feel the pain of those handicapped persons. Viewers while viewing the blind students might feel pity and sympathy but the film possesses a considerable portion of dialogues and scenes where these feelings of the viewers are sidelined by the dominance of self-confidence and self-reliance. Here, the love story set in emotional surroundings applies metaphors to describe the depth sidelining the normal life love story where the beauty is judged by eyes. Despite the unique touch orchestrated by this film, ‘Sparsh’ has become a classic film. In fact, ‘Sparsh’ is a touching film made with touching vision. Sai Paranjape's realistic vision to tell this beautiful and realistic narrative is admirable because her journey was not through any commercial way. She has kept the essence and realism alive which is worth watching. After all, to be precise, ‘Sparsh’ is a fantastic film. This film is an example of real cinematic art form. It also has an authentic flavour of Indian film culture. This is pure and really heartfelt. The film has exhibited the touch that has been realized by the touch of celluloid, the touch of the Director and Actors and Actresses. ‘Sparsh’ (Touch) has shown us that human beings are ready to touch and be touched.
A Survey of Techniques for Optimizing Transformer Inference
No full textRecent years have seen a phenomenal rise in performance and applications of transformer neural networks. The family of transformer networks, including Bidirectional Encoder Representations from Transformer (BERT), Generative Pretrained Transformer (GPT) and Vision Transformer (ViT), have shown their effectiveness across Natural Language Processing (NLP) and Computer Vision (CV) domains. Transformer-based networks such as ChatGPT have impacted the lives of common men. However, the quest for high predictive performance has led to an exponential increase in transformers' memory and compute footprint. Researchers have proposed techniques to optimize transformer inference at all levels of abstraction. This paper presents a comprehensive survey of techniques for optimizing the inference phase of transformer networks. We survey techniques such as knowledge distillation, pruning, quantization, neural architecture search and lightweight network design at the algorithmic level. We further review hardware-level optimization techniques and the design of novel hardware accelerators for transformers. We summarize the quantitative results on the number of parameters/FLOPs and accuracy of several models/techniques to showcase the tradeoff exercised by them. We also outline future directions in this rapidly evolving field of research. We believe that this survey will educate both novice and seasoned researchers and also spark a plethora of research efforts in this field.This preprint of Chitty-Venkata, K.T., Mittal, S., Emani, M., Vishwanath, V., Somani, A.K., A Survey of Techniques for Optimizing Transformer Inference. Is available at ArXiv (arXiv:2307.07982) https://doi.org/10.48550/arXiv.2307.07982. Posted with permission. CC BY-NC-ND 4.0 DEED Attribution-NonCommercial-NoDerivs 4.0 International. Published as Chitty-Venkata, Krishna Teja, Sparsh Mittal, Murali Emani, Venkatram Vishwanath, and Arun K. Somani. "A survey of techniques for optimizing transformer inference." Journal of Systems Architecture (2023): 102990.
doi: https://doi.org/10.1016/j.sysarc.2023.10299
A survey on evaluating and optimizing performance of Intel Xeon Phi
No full textIntel's Xeon Phi combines the parallel processing power of a many-core accelerator with the programming ease of CPUs. In this paper, we present a survey of works that study the architecture of Phi and use it as an accelerator for a broad range of applications. We review performance optimization strategies as well as the factors that bottleneck the performance of Phi. We also review works that perform comparison or collaborative execution of Phi with CPUs and GPUs. This paper will be useful for researchers and developers in the area of computer-architecture and high-performance computing
A survey of techniques for dynamic branch prediction
No full textBranch predictor (BP) is an essential component in modern processors since high BP accuracy can improve performance and reduce energy by decreasing the number of instructions executed on wrong-path. However, reducing the latency and storage overhead of BP while maintaining high accuracy presents significant challenges. In this paper, we present a survey of dynamic branch prediction techniques. We classify the works based on key features to underscore their differences and similarities. We believe this paper will spark further research in this area and will be useful for computer architects, processor designers, and researchers
A Survey of Value Prediction Techniques for Leveraging Value Locality
No full textValue locality (VL) refers to recurrence of values in a memory structure and value prediction (VP) refers
to predicting VL and leveraging it for diverse optimizations. VP holds the promise of exceeding truedata
dependencies and provide performance and bandwidth advantages in both single- and multi-threaded
applications. Fully exploiting the potential of VL, however, requires addressing several challenges, such
as achieving high accuracy and coverage, reducing hardware and latency overheads, etc. In this paper, we
present a survey of techniques for leveraging value locality. We categorize the research works based on key
parameters to provide insights and highlight similarities and differences. This paper is expected to be useful
for researchers, processor architects and chip-designers
A Survey of Soft-Error Mitigation Techniques for Non-Volatile Memories
No full textNon-volatile memories (NVMs) offer superior density and energy characteristics compared to the conventional memories; however, NVMs suffer from severe reliability issues that can easily eclipse their energy efficiency advantages. In this paper, we survey architectural techniques for improving the soft-error reliability of NVMs, specifically PCM (phase change memory) and STT-RAM (spin transfer torque RAM). We focus on soft-errors, such as resistance drift and write disturbance, in PCM and read disturbance and write failures in STT-RAM. By classifying the research works based on key parameters, we highlight their similarities and distinctions. We hope that this survey will underline the crucial importance of addressing NVM reliability for ensuring their system integration and will be useful for researchers, computer architects and processor designers
A Survey of Techniques for Cache Partitioning in Multicore Processors
No full textAs the number of on-chip cores and memory demands of applications increase, judicious management of cache resources has become not merely attractive but imperative. Cache partitioning, that is, dividing cache space between applications based on their memory demands, is a promising approach to provide capacity benefits of shared cache with performance isolation of private caches. However, naively partitioning the cache may lead to performance loss, unfairness, and lack of quality-of-service guarantees. It is clear that intelligent techniques are required for realizing the full potential of cache partitioning. In this article, we present a survey of techniques for partitioning shared caches in multicore processors. We categorize the techniques based on important characteristics and provide a bird’s eye view of the field of cache partitioning
A Survey of ReRAM-Based Architectures for Processing-In-Memory and Neural Networks
No full textAs data movement operations and power-budget become key bottlenecks in the design of computing systems, the interest in unconventional approaches such as processing-in-memory (PIM), machine learning (ML), and especially neural network (NN)-based accelerators has grown significantly. Resistive random access memory (ReRAM) is a promising technology for efficiently architecting PIM- and NN-based accelerators due to its capabilities to work as both: High-density/low-energy storage and in-memory computation/search engine. In this paper, we present a survey of techniques for designing ReRAM-based PIM and NN architectures. By classifying the techniques based on key parameters, we underscore their similarities and differences. This paper will be valuable for computer architects, chip designers and researchers in the area of machine learnin
Versatile question answering systems: seeing in synthesis
No full textInternational audienceRecent advances in massive information storage and growth of internet have led to increased necessity of tools such as search engines and QA systems to get meaningful answers from the vast amount of information. The complex questions appearing in real-life generally require multiple techniques or sub-division of question at various levels. Several practical systems have been developed to explore this. This paper reviews state-of-art QA systems which provide enhanced and versatile functionality at various levels in their architecture and then makes the following contributions: 1 it provides useful overview of research trends and recent developments in the area of QA 2 the paper introduces and defines basic design parameters for any QA system 3 it resolves semantic heterogeneity by clarifying the meaning and context in which different terms are used by different researchers 4 it classifies the existing QA systems in broad groups, based on the point at which versatility (multiplicity) is introduced/handled in the system 5 by developing a unified view of existing frontiers of QA systems, it provides clear directions for future research and development in the area
A Survey of Techniques for Architecting TLBs
No full text“Translation lookaside buffer” (TLB) caches virtual to physical address translation information and is used\ud
in systems ranging from embedded devices to high-end servers. Since TLB is accessed very frequently\ud
and a TLB miss is extremely costly, prudent management of TLB is important for improving performance\ud
and energy efficiency of processors. In this paper, we present a survey of techniques for architecting and\ud
managing TLBs. We characterize the techniques across several dimensions to highlight their similarities and\ud
distinctions. We believe that this paper will be useful for chip designers, computer architects and system\ud
engineers
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