1,721,113 research outputs found
An Approach to the Analysis of the CMOS Differential Stage With Active Load and Single-Ended Output
No full textThe complementary metal-oxide-semiconductor (CMOS) differential amplifier with active load and single-ended output is one of the most widespread analog building blocks in modern mixed-signal circuits for signal processing applications, because of its good performance in terms of common-mode rejection and voltage gain, combined with an extremely simple circuit structure, which performs directly differential to single-ended conversion. The authors present a straightforward approach to studying the behavior of such a simple circuit and try to explain some of its features in an intuitive way without resorting to tedious calculations. In particular, this study considers the do operating point and the common- and differential-mode voltage gains, and the results of the proposed analysis are in good agreement with those provided by both accurate analytical solution and simulation of the circuit. Among the other results, this approach emphasizes some interesting, though very often neglected, aspects of the circuit behavior
Relative robustness against process fluctuations of basic building blocks for analog front-end of particle detectors
No full textThe large number of channels (15.7 millions), needed
for the silicon pixel detector under development for the
ALICE ITS, requires a careful study of the statistical
fluctuations of the front-end electronics performance.
By means of classical techniques, such as the
Principal Component Analysis, and of new ones used to
perform a “realistic” worst case analysis, various
configurations of basic CMOS amplifier stages have been
compared to evaluate the relative robustness of their
performance against manufacturing fluctuations.
To validate the simulated results on a significant
statistical sample, a test pattern containing these basic
building blocks has been designed and implemented in a
0.35mm process. In this work we present the theoretical
results, achieved by applying the proposed Worst Case
Analysis technique. The characterisation of the test chip
prototypes is currently in progress
Interfacing a SiPM to a Current-mode Front-end: Effects of the Coupling Inductance
No full textThe design of front-end electronics for SiPM detectors poses some peculiar constraints which call for dedicated architectures that may remarkably differ from the commonly used ones for other solid state detectors. In particular, present day SiPM’s may have a number of microcells as high as 90,000. This may pose serious problems in terms of dynamic range of the output signal, especially when low voltage technologies are employed to implement the FE. Besides that, SiPM’s are inherently high speed devices characterized by large equivalent capacitance CDET. All the above characteristics indicate a current mode architecture as the most suitable one to interface this kind of devices. In the past several different topologies have been proposed in the literature most of them aiming at realizing the lowest possible value of input resistance, Rin, in the perspective of limiting the time constant in = RinCDET associated to the input node of the amplifier, which is usually deemed to be the dominant parameter affecting the dynamic performance of the FE. In this contribution we show that this is not the case in real situations and that there is an optimum range of values for the input resistance in dependence of the particular SiPM and of the interconnection parasitics, thus avoiding the need of realizing arbitrarily low values of input resistance that would also imply unnecessary high power dissipation and additional electronic noise, due to the high bias currents required in the input stage of the preamplifier. The results of the study, performed on a handly 2nd order SiPM model, are confirmed by both circuit simulations on a more accurate 4th order model and by lab experiments on commercially available devices
Silicon pin detector with integrated JFET-based source follower
No full textA pin photodiode monolithically integrated with a bias resistor and a JFET-based source follower is presented. Results from static and dynamic characterisation of the structure are reported, together with SPICE simulations used to design an optimised device which can be fabricated in the same technology. This structure can be employed as a pixel in linear X-ray scanners for non-destructive inspection
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Dc characterization of lateral bipolar devices in standard CMOS technology: a new model for base current partitioning
No full textAs is generally known, compared with MOSFETs bipolar transistors provide better performance in terms of small signal transconductance, intrinsic cut-off frequency and noise characteristics, at the cost of a more expensive technology. A good compromise between the low costs proper of standardCMOS technology and the excellent performance typical of bipolardevices can be achieved by using bipolar transistors derived from MOS structures. Naturally suitable models combined with efficient parameter extraction techniques are mandatory to provide designers with reliable simulation tools. Adc parameter extraction procedure for a PNP lateral transistor realized in astandardCMOS technology based on an existing composite circuit model is presented here. The extraction results provide accurate fitting between measured and simulated data for different operating regions without resort to numerical optimization, thus preserving the physical meaning of the extracted parameters and retaining a good correlation with process variations
Variations on the Author
Full text link“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
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