36 research outputs found
RD53 Collaboration and CHIPIX65 Project for the development of an innovative Pixel Front End Chip for HL-LHC
No full textBulk damage in proton irradiated JFET transistors and charge preamplifiers on high resistivity silicon
No full textNovel active signal compression in low-noise analog readout at future X-ray FEL facilities
No full textThis work presents the design of a low-noise front-end implementing a novel active signal compression technique. This feature can be exploited in the design of analog readout channels for application to the next generation free electron laser (FEL) experiments. The readout architecture includes the low-noise charge sensitive amplifier (CSA) with dynamic signal compression, a time variant shaper used to process the signal at the preamplifier output and a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC). The channel will be operated in such a way to cope with the high frame rate (exceeding 1 MHz) foreseen for future XFEL machines. The choice of a 65 nm CMOS technology has been made in order to include all the building blocks in the target pixel pitch of 100 mu m. This work has been carried out in the frame of the PixFEL Project funded by the Istituto Nazionale di Fisica Nucleare (INFN), Italy
Novel active signal compression in low-noise analog readout at future X-ray FEL facilities
No full textThis work presents the design of a low-noise front-end implementing a novel active signal compression technique. This feature can be exploited in the design of analog readout channels for application to the next generation free electron laser (FEL) experiments. The readout architecture includes the low-noise charge sensitive amplifier (CSA) with dynamic signal compression, a time variant shaper used to process the signal at the preamplifier output and a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC). The channel will be operated in such a way to cope with the high frame rate (exceeding 1 MHz) foreseen for future XFEL machines. The choice of a 65 nm CMOS technology has been made in order to include all the building blocks in the target pixel pitch of 100 mu m. This work has been carried out in the frame of the PixFEL Project funded by the Istituto Nazionale di Fisica Nucleare (INFN), Italy
28 nm CMOS analog front-end channels for future pixel detectors
No full textThis work discusses the design, carried out in the framework of the INFN Falaphel project, of analog front-end circuits for future, high-rate pixel detector applications. In particular, two front-end architectures are being developed, one with Time-over-Threshold (ToT) digitization of the input signal and the other based on an in-pixel flash ADC featuring a novel, clocked comparator conceived to dramatically reduce the threshold dispersion of the front-end. The paper includes a description of the analog processors being developed. The main analog performance parameters, as obtained from circuit simulations and including equivalent noise charge and threshold dispersion, are reported
CHIPIX65: Developments on a new generation pixel readout ASIC in CMOS 65 nm for HEP experiments
No full textPixel detectors at HL-LHC experiments or other future experiments are facing new challenges, especially in terms of unprecedented levels of radiation and particle flux. This paper describes the progress made by the CHIPIX65 project of INFN for the development of a new generation readout ASIC using CMOS 65 nm technology
RD53 Collaboration and CHIPIX65 Project for the development of an innovative Pixel Front End Chip for HL-LHC
No full textPixel detectors at HL-LHC experiments will be exposed to unprecedented level of radiation and particle flux. This paper describes the program of development of an innovative pixel chip using a CMOS 65nm technology for the first time in HEP community, for experiments with extreme particle rates and radiation at future High Energy Physics colliders. The RD53 collaboration effort is described together with the CHIPIX65 INFN project
Design of analog front-ends for the RD53 demonstrator chip
No full textThe RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment
The SuperB silicon vertex tracker
No full textThe SuperB asymmetric e+e− collider, to be built near the INFN National Frascati Laboratory in Italy, has been designed to deliver a luminosity greater than 1036 cm−2 s−1 with moderate beam currents, allowing precision measurements in the flavour sector sensitive to New Physics. The conceptual design of the Silicon Vertex Tracker for the SuperB Detector is presented, based on double-sided silicon strip detectors for the outer layers, with the addition of an innermost Layer 0 close to the interaction point, with low material budget and capable of sustaining a background rate of several MHz/cm2
SuperB: A High-Luminosity Asymmetric Super Flavour Factory : Conceptual Design Report
No full textThe physics objectives of SuperB, an asymmetric electron-positron collider with a luminosity above 10^36/cm^2/s are described, together with the conceptual design of a novel low emittance design that achieves this performance with wallplug power comparable to that of the current B Factories, and an upgraded detector capable of doing the physics in the SuperB environment.The physics objectives of SuperB, an asymmetric electron-positron collider with a luminosity above 10^36/cm^2/s are described, together with the conceptual design of a novel low emittance design that achieves this performance with wallplug power comparable to that of the current B Factories, and an upgraded detector capable of doing the physics in the SuperB environment
