79 research outputs found
A study of charm production in proton proton interactions at s**(1/2) = 62-GeV with a forward k- trigger
No full textThe production of charm mesons D('*) and D and their subsequent decays D('*+) (--->) D('0)(pi)('+) and D('0) (--->) K('-)(pi)('+) have been observed in proton-proton interactions at the CERN Intersecting Storage Rings. Using published data for inclusive K('-) and p production cross sections as normalization, the D('*+) production cross section is estimated. For a model with the D('*+) produced with a Feynman-x (x(,F)) distribution of the form (1-x(,F))('2) and a transverse momentum distribution of the form P(,t)*exp(-P(,t)('2)), the D('*('+)) production cross section is estimated to be 23.5 (+OR-) 8.4 (mu)b;This measurement is approximately the same as measurements by other experiments of charm meson production at lower energies. Two other experiments have measured the D('0) production cross section at our energy, and obtained a result more than ten times higher than ours. Thus, our measurement provides a possible resolution to what had been an unclear situation in regard to the energy dependence of charm production; ('1)DOE Report IS-T-1145. This work was performed under crontract No. W-7405-Eng-82 with the U.S. Department of Energy.</p
On-Chip time measurement architectures and implementation
No full textIn recent years, system on chip (SoC) devices have become increasingly popular in many applications, such as automotive, signal processing, portable electronic devices and communication products. This has led to more functionality being integrated onto a single piece of silicon. As the level of technology decreases down to smaller geometries, not only has the design become more complicated but also the verification of such devices has become significantly complex that it has led to stringent timing requirements being placed on such devices. With the continuing integration and speed scaling to higher frequencies into the low giga Hertz range, limitations in the effectiveness of traditional production testing have been introduced. The increase in cost of automatic test equipment (ATE) and the fact that the electrical distance between the tester and the embedded core under test (CUT) has got wider has made the verification of such devices challenging.To alleviate this cost test problem, this research investigates the design and methods associated with high resolution on-chip time measurement systems and proposes the design of a low cost, high resolution, programmable time measurement architecture for characterizing on-chip time measurements. This new architecture is based on the time-to-digital conversion (TDC) method and uses the dual-slope technique to perform the timing measurement. The proposed architecture can perform a number of different types of time measurements, such as rise and fall time, pulse width and propagation delay type measurements, without the need for additional circuitry or circuit duplication that would add to the overall cost of the time measurement architecture. Each of the critical building blocks are analysed and a description of the final implementation of a prototype chip using a 0.12µm CMOS process is described.As the on-chip clock speeds of high performance VLSI devices increase into the tens of Gigahertz range, time measurement architectures with timing resolutions of tens of femtoseconds will be required. Current high resolution time measurements architectures based on vernier and flash time measurement architectures use latches and flip-flops in the main timing measurement technique and can suffer from the inherited metastability phenomenon. To address this problem, current research solutions are analysed in this thesis and an on-chip time measurement architecture that is also based on the time-to-digital conversion method but uses the homodyne technique is proposed. The architecture is described and finally simulations using transistors based on a 0.12µm CMOS process are presented and suggest that timing resolutions in the tens of femtosecond range are attainable
Performance of the HPC calorimeter in DELPHI
No full textThe performance of the High-density Projection Chamber (HPC), the barrel electromagnetic calorimeter of the DELPHI experiment, is described. The detector adopts the time projection technique in order to obtain exceptionally fine spatial granularity in the three coordinates (~ 2 x 20 mrad2 in θ x π with nine samplings along the shower axes), using a limited number of readout channels (18,432). Among the various topics concerning the HPC construction and operation, major emphasis is given to the aspects related to the calibration in energy of the calorimeter, based mainly on the analysis of the detector response to 83mKr decays, and to the treatment of ageing in the readout proportional counters. © 1995 IEEE
MEASUREMENT OF THE MASS AND WIDTH OF THE Z0 PARTICLE FROM MULTI - HADRONIC FINAL STATES PRODUCED IN e+ e- ANNIHILATIONS
No full textFirst measurements of the mass and width of the Z0 performed at the newly commissioned LEP Collider by the DELPHI Collaboration are presented. The measuements are derived from the study of multihadronic final states produced in e+e- annihilations at several energies around the Z0 mass. The values found for the mass and width are M(Z0)=91.06±0.09 (stat) ±0.045 (syst.) GeV and Γ(Z0)=2.42±0.21 (stat.) GeV respectively, froma three-parameter fit to the line shape. A two-parameter fit in the framework of the standard model yields for the number of light neutrino species Nν=2.4±0.4 (stat.) ±0.5 (syst.)0SCOPUS: ar.jinfo:eu-repo/semantics/publishe
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