160,811 research outputs found
Musica e scena: considerazioni di Luca Ronconi sulla regia lirica
No full textLe riflessioni critiche di Luca Ronconi sulla regia lirica.Music and stage: Luca Ronconi opera director
Heart rate variability and target organ damage in hypertensive patients
No full textBackground:
We evaluated the association between linear standard Heart Rate Variability (HRV) measures and vascular, renal and cardiac target organ damage (TOD).
Methods:
A retrospective analysis was performed including 200 patients registered in the Regione Campania network (aged 62.4 ± 12, male 64%). HRV analysis was performed by 24-h holter ECG. Renal damage was assessed by estimated glomerular filtration rate (eGFR), vascular damage by carotid intima-media thickness (IMT), and cardiac damage by left ventricular mass index.
Results:
Significantly lower values of the ratio of low to high frequency power (LF/HF) were found in the patients with moderate or severe eGFR (p-value < 0.001). Similarly, depressed values of indexes of the overall autonomic modulation on heart were found in patients with plaque compared to those with a normal IMT (p-value <0.05). These associations remained significant after adjustment for other factors known to contribute to the development of target organ damage, such as age. Moreover, depressed LF/HF was found also in patients with left ventricular hypertrophy but this association was not significant after adjustment for other factors.
Conclusions:
Depressed HRV appeared to be associated with vascular and renal TOD, suggesting the involvement of autonomic imbalance in the TOD. However, as the mechanisms by which abnormal autonomic balance may lead to TOD, and, particularly, to renal organ damage are not clearly known, further prospective studies with longitudinal design are needed to determine the association between HRV and the development of TOD
Luca Ronconi e gli anni del Piccolo Teatro di Milano
No full textIl percorso artistico di Luca Ronconi al Piccolo Teatro di Milano 2000-2015.The theatrical work of Luca Ronconi for the Piccolo Teatro di Milano 2000-2015
Evidencing the "robot phase transition" in experimental human-algorithmic markets
No full textJohnson, Zhao, Hunsader, Meng, Ravindar, Carran, and Tivnan (2012) recently suggested the existence of a phase transition in the dynamics of financial markets in which there is free interaction between human traders and algorithmic trading systems ("robots"). Above a particular time-threshold, humans and robots trade with one another; below the threshold all transactions are robot-to-robot. We refer to this abrupt system transition as the "robot phase transition". Here, we conduct controlled experiments where human traders interact with 'robot' trading agents in minimal models of electronic financial markets to see if correlates of the two regimes suggested by Johnson et al. (2012) occur in such laboratory conditions. Our results indicate that when trading robots act on a super-human timescale, the market starts to fragment, with statistically lower human-robot interactions than we would expect from a fully mixed market. We tentatively conclude that this is the first empirical evidence for the robot phase transition occurring under controlled experimental conditions
Ai margini dell'abitare. Strutture e servizi di contrasto alla povertà nella Provincia di Firenze
No full textColloquio con Luca Canali su Fellini-Satyricon
No full textInterview with Luca Canali, a classical scholar who was Fellini's consultant for Latin language and Roman antiquities on the set of Fellini-Satyricon
Título: Origen y milagros del Santísimo Cristo de Luca
No full textEs trad. de De inventione, revelatione ac translatione sacratissimi vultus de Luca, con la que está encuadernadaCopia digital. Madrid : Ministerio de Cultura. Subdirección General de Coordinación Bibliotecaria, 2006Tít. de la cub.: "Origen y milagros del Smo. Xto. de Luca: es de la hermandad de S. Cosme y S.Damián y Jesus de Luca sita en los Reales Alcázares de Toledo desde el imperio de Carlos quinto que dio en la hermandad el Jesus de Luca que oy está en el combento de Capuchinos de esta ciudad de Toledo en el corateral [sic] del Evangelio propio de dicha hermandad"Colofón (h. XXXIXv.): "Tradúxose de latín es castellano para que sea más notorio... Trasladólo de papel en pergamino por mandado de la cofradía Diego Fernández scriptor de libros y cofrade de la dicha cofradía. Anno a nativitate Domini nostri Iesu Christi mill DXXXVII a XX de nouiembre. E Toledo. Dios le tenga de su mano por el trabajo."Cuadernos de 8 h.; reclamos; foliación a tinta roja de la misma mano que el texto; pautado a tinta roja diluída; caja de escr.: 17 x 11 cmIniciales rojas y azules con rasgueo
System-on-chip Computing and Interconnection Architectures for Telecommunications and Signal Processing
No full textThis dissertation proposes novel architectures and design techniques targeting SoC building blocks for telecommunications and signal processing applications.
Hardware implementation of Low-Density Parity-Check decoders is approached at both the algorithmic and the architecture level. Low-Density Parity-Check codes are a promising coding scheme for future communication standards due to their outstanding error correction performance.
This work proposes a methodology for analyzing effects of finite precision arithmetic on error correction performance and hardware complexity. The methodology is throughout employed for co-designing the decoder. First, a low-complexity check node based on the P-output decoding principle is designed and characterized on a CMOS standard-cells library. Results demonstrate implementation loss below 0.2 dB down to BER of 10^{-8} and a saving in complexity up to 59% with respect to other works in recent literature. High-throughput and low-latency issues are addressed with modified single-phase decoding schedules. A new "memory-aware" schedule is proposed requiring down to 20% of memory with respect to the traditional two-phase flooding decoding. Additionally, throughput is doubled and logic complexity reduced of 12%. These advantages are traded-off with error correction performance, thus making the solution attractive only for long codes, as those adopted in the DVB-S2 standard. The "layered decoding" principle is extended to those codes not specifically conceived for this technique. Proposed architectures exhibit complexity savings in the order of 40% for both area and power consumption figures, while implementation loss is smaller than 0.05 dB.
Most modern communication standards employ Orthogonal Frequency Division Multiplexing as part of their physical layer. The core of OFDM is the Fast Fourier Transform and its inverse in charge of symbols (de)modulation. Requirements on throughput and energy efficiency call for FFT hardware implementation, while ubiquity of FFT suggests the design of parametric, re-configurable and re-usable IP hardware macrocells. In this context, this thesis describes an FFT/IFFT core compiler particularly suited for implementation of OFDM communication systems. The tool employs an accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results are presented for two deep sub-micron standard-cells libraries (65 and 90 nm) and commercially available FPGA devices. Compared with other FFT core compilers, the proposed environment produces macrocells with lower circuit complexity and same system level performance (throughput, transform size and numerical accuracy).
The final part of this dissertation focuses on the Network-on-Chip design paradigm whose goal is building scalable communication infrastructures connecting hundreds of core. A low-complexity link architecture for mesochronous on-chip communication is discussed. The link enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. The proposed architecture reaches a maximum clock frequency of 1 GHz on 65 nm low-leakage CMOS standard-cells library. In a complex test case with a full-blown NoC infrastructure, the link overhead is only 3% of chip area and 0.5% of leakage power consumption.
Finally, a new methodology, named metacoding, is proposed. Metacoding generates correct-by-construction technology independent RTL codebases for NoC building blocks. The RTL coding phase is abstracted and modeled with an Object Oriented framework, integrated within a commercial tool for IP packaging (Synopsys CoreTools suite). Compared with traditional coding styles based on pre-processor directives, metacoding produces 65% smaller codebases and reduces the configurations to verify up to three orders of magnitude
Un Moyen Âge sans censure ? Réponse à Alain Boureau
No full textBianchi Luca. Un Moyen Âge sans censure ? Réponse à Alain Boureau. In: Annales. Histoire, Sciences Sociales. 57ᵉ année, N. 3, 2002. pp. 733-743
Le portrait du poète: Baudelaire par Gautier
No full textPIETROMARCHI Luca. Le portrait du poète : Baudelaire par Gautier. In: Cahiers de l'Association internationale des études francaises, 2003, n°55. pp. 519-531
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