734 research outputs found
Xenoastrosphaeriella aquatica sp. nov. from freshwater habitat in Yunnan Province, China
No full textLuo, Zong-Long, Bao, Dan-Feng, Li, Long-Li, Luan, Sha, Su, Hong-Yan (2022): Xenoastrosphaeriella aquatica sp. nov. from freshwater habitat in Yunnan Province, China. Phytotaxa 544 (2): 193-200, DOI: 10.11646/phytotaxa.544.2.
FIGURE 2 in Xenoastrosphaeriella aquatica sp. nov. from freshwater habitat in Yunnan Province, China
No full textFIGURE 2. Xenoastrosphaeriella aquatica (KUN-HKAS 115792, holotype). a, b Appearance of ascomata on host substrate. c Pseudoparaphyses. d Vertical section through ascoma. e, f Parts of peridium. g–l Asci. m–r Ascospores. Scale bars: d = 200 μm, e = 50 μm, f–l = 30 μm, c, m–r = 20μm.Published as part of Luo, Zong-Long, Bao, Dan-Feng, Li, Long-Li, Luan, Sha & Su, Hong-Yan, 2022, Xenoastrosphaeriella aquatica sp. nov. from freshwater habitat in Yunnan Province, China, pp. 193-200 in Phytotaxa 544 (2) on page 197, DOI: 10.11646/phytotaxa.544.2.5, http://zenodo.org/record/650389
Performance Analysis of Modified SHA-3
No full textAbstractSecurity services have become an inseparable feature of almost all digital transactions. A crucial module of these scheme isintegrity, which is performed using a cryptographic hash function. Secure Hash Algorithm can be an efficient hashing technique.SHA-3 is the most recent and efficient Secure Hash Algorithm. Keccak has been chosen as the official algorithm for SHA-3 in2012. In this paper we propose a modification on the design of Secure Hash Algorithm (SHA-3) on Xilinx Field ProgrammableGate Array (FPGA) device. In order to provide reliable architecture for this algorithm, a concurrent error tolerant scheme forSHA-3 is used. A system based on the combination of SHA-3 and error tolerant scheme is also described. Simulation resultsshows, an efficiency in area and delay of SHA-3 designs
A High-Performance Multimem SHA-256 Accelerator for Society 5.0
No full textThe development of a low-cost high-performance secure hash algorithm (SHA)-256 accelerator has recently received extensive interest because SHA-256 is important in widespread applications, such as cryptocurrencies, data security, data integrity, and digital signatures. Unfortunately, most current researches have focused on the performance of the SHA-256 accelerator but not on a system level, in which the data transfer between the external memory and accelerator occupies a large time fraction. In this paper, we solve the state-of-art problem with a novel SHA-256 architecture named the multimem SHA-256 accelerator that achieves high performance at the system on chip (SoC) level. Notably, our accelerator employs three novel techniques, the pipelined arithmetic logic unit (ALU), multimem processing element (PE), and shift buffer in shift buffer out (SBi-SBo), to reduce the critical path delay and significantly increase the processing rate. Experiments on a field-programmable gate array (FPGA) and an application-specific integrated circuit (ASIC) show that the proposed accelerator achieves significantly better processing rate and hardware efficiency than previous works. The accelerator accuracy is verified on a real hardware platform (FPGA ZCU102). The accelerator is synthesized and laid out with 180 nm complementary metal oxide semiconductor (CMOS) technology with a chip sized 8.5mm × 8.5mm, consumes 1.86 W, and provides a maximum processing rate of 40.96 Gbps at 80 MHz and 1.8 V.With FPGA Xilinx 16 nm FinFET technology, the accelerator processing rate is as high as 284 Gbps
Security and usability of standard has hfunctions, in particular MD-5, SHA-1 and SHA-2
No full textTitle: Security and usability of standard hash functions, in particular MD-5, SHA-1 and SHA-2 Author: Galaczová Barbora Department: Department of Algebra Supervisor: Doc. RNDr. Tůma Jiří, DrSc., Department of Algebra Consultant: Ing. Budiš Petr, Ph.D. Abstract: In the present work we try to digestedly describe standard hash functions, in particular MD-5, SHA-1 and SHA-2. We describe resume of existing attacks on these hash functions. We closely focused on MD-5 collision attacks, because the other hash function collision attacks result from these. Next we describe posibilities of practical usage of hash function collisions, in particular into the qualified certificates area and possible threats. At the end to the present work we describe new hash functions, which could replace current hash functions. This work also contains software to calculate MD-5 hash and search it`s collisions. The software is based on method invented by Czech cryptoanalytist Vlastimil Klíma. Keywords: hash function, collision, qualified certificate, security
Cryptanalysis of Dynamic SHA(2)
No full textIn this paper, we analyze the hash functions Dynamic SHA and Dynamic SHA2, which have been selected as first round candidates in the NIST hash function competition. These hash functions rely heavily on data-dependent rotations, similar to certain block ciphers, e.g., RC5. Our analysis suggests that in the case of hash functions, where the attacker has more control over the rotations, this approach is less favorable than in block ciphers. We present practical, or close to practical, collision attacks on both Dynamic SHA and Dynamic SHA2. Moreover, we present a preimage attack on Dynamic SHA that is faster than exhaustive search. © 2009 Springer-Verlag Berlin Heidelberg.sponsorship: Supported by the Swiss National Science Foundation, project no. 113329. This author was supported by the France Telecom chaire. F.W.O. Research Assistant, Fund for Scientific Research Flander s (Belgium) (Swiss National Science Foundation|113329, France Telecom chaire, Scientific Research)status: Publishe
Design & Characterization of SHA 3- 256 Bit IP Core
No full textAbstractIn the era of internet and computer networking the need for security have increased rapidly. Various crypto algorithms are used for secured data transmission and reception through the network, of which hash function possess a key role in various cryptographic protocols. Keccak algorithm is the winner of SHA-3 competition conducted by NIST. SHA-3 consists of different variant such as 224, 256, 384 and 512 bit. This paper discuss the design and implementation of SHA-3 256- bit core. The core is designed using Verilog HDL and prototyped using Xilinx® Virtex®-6FPGA
A High-Performance Multimem SHA-256 Accelerator for Society 5.0
No full textThe development of a low-cost high-performance secure hash algorithm (SHA)-256 accelerator has recently received extensive interest because SHA-256 is important in widespread applications, such as cryptocurrencies, data security, data integrity, and digital signatures. Unfortunately, most current researches have focused on the performance of the SHA-256 accelerator but not on a system level, in which the data transfer between the external memory and accelerator occupies a large time fraction. In this paper, we solve the state-of-art problem with a novel SHA-256 architecture named the multimem SHA-256 accelerator that achieves high performance at the system on chip (SoC) level. Notably, our accelerator employs three novel techniques, the pipelined arithmetic logic unit (ALU), multimem processing element (PE), and shift buffer in shift buffer out (SBi-SBo), to reduce the critical path delay and significantly increase the processing rate. Experiments on a field-programmable gate array (FPGA) and an application-specific integrated circuit (ASIC) show that the proposed accelerator achieves significantly better processing rate and hardware efficiency than previous works. The accelerator accuracy is verified on a real hardware platform (FPGA ZCU102). The accelerator is synthesized and laid out with 180 nm complementary metal oxide semiconductor (CMOS) technology with a chip sized 8.5mm × 8.5mm, consumes 1.86 W, and provides a maximum processing rate of 40.96 Gbps at 80 MHz and 1.8 V.With FPGA Xilinx 16 nm FinFET technology, the accelerator processing rate is as high as 284 Gbps.journal articl
Uma solução de autenticação fim a fim para o LDP (Label Distribution Protocol)
No full textDissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico. Programa de Pós-Graduação em Ciência da Computação.Este trabalho propõe uma solução de autenticação para o protocolo LDP (Label Distribution Protocol) que tem por objetivo autenticar, em um escopo fim a fim, o estabelecimento de um LSP (Label Switching Path) entre um LSR (Label Switching Router) de Ingresso e o seu respectivo LSR de Egresso. Objetiva-se suprir a deficiência do protocolo LDP de não possuir um mecanismo de autenticação fim a fim definido, aplicável entre LSRs não-adjacentes. Conforme foi verificado pelo levantamento de trabalhos correlatos, atualmente é desconhecida uma solução de autenticação semelhante, que efetivamente atenda o propósito de autenticar num escopo fim a fim, o estabelecimento de LSPs no protocolo LDP. Dessa forma a solução deste trabalho é inédita no seu escopo de aplicação. A solução foi planejada para ambientes onde LSPs atravessam múltiplos domínios externos, não confiáveis entre si, e que por isso necessitam de um mecanismo de autenticação durante o estabelecimento dos LSPs. A solução faz uso de um mecanismo de autenticação, baseado em criptografia assimétrica (chave pública e privada), anexado a cada mensagem LDP. Este mecanismo possibilita ao LSR receptor verificar e autenticar o originador da mensagem LDP. Adicionalmente a solução provê integridade de dados através de um mecanismo de resumo de mensagens (hash) e também protege contra ataques de repetição através da inserção de um nonce às mensagens LDP
Double SHA-256 Hardware Architecture with Compact Message Expander for Bitcoin Mining
No full textIn the Bitcoin network, computing double SHA-256 values consumes most of the network energy. Therefore, reducing the power consumption and increasing the processing rate for the double SHA-256 algorithm is currently an important research trend. In this paper, we propose a high-data-rate low-power hardware architecture named the compact message expander (CME) double SHA-256. The CME double SHA-256 architecture combines resource sharing and fully unrolled datapath technologies to achieve both a high data rate and low power consumption. Notably, the CME algorithm utilizes the double SHA-256 input data characteristics to further reduce the hardware cost and power consumption. A review of the literature shows that the CME algorithm eliminates at least 9.68% of the 32-bit XOR gates, 16.49% of the 32-bit adders, and 16.79% of the registers required to calculate double SHA-256. We synthesized and laid out the CME double SHA-256 using CMOS 0.18 μm technology. The hardware cost of the synthesized circuit is approximately 13.88% less than that of the conventional approach. The chip layout size is 5:9mm×9mm, and the correctness of the circuit was verified on a real hardware platform (ZCU 102). The throughput of the proposed architecture is 61.44 Gbps on an ASIC with Rohm 180nm CMOS standard cell library and 340 Gbps on a FinFET FPGA 16nm Zynq UltraScale+ MPSoC ZCU102
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