457 research outputs found
System-on-chip Computing and Interconnection Architectures for Telecommunications and Signal Processing
No full textThis dissertation proposes novel architectures and design techniques targeting SoC building blocks for telecommunications and signal processing applications.
Hardware implementation of Low-Density Parity-Check decoders is approached at both the algorithmic and the architecture level. Low-Density Parity-Check codes are a promising coding scheme for future communication standards due to their outstanding error correction performance.
This work proposes a methodology for analyzing effects of finite precision arithmetic on error correction performance and hardware complexity. The methodology is throughout employed for co-designing the decoder. First, a low-complexity check node based on the P-output decoding principle is designed and characterized on a CMOS standard-cells library. Results demonstrate implementation loss below 0.2 dB down to BER of 10^{-8} and a saving in complexity up to 59% with respect to other works in recent literature. High-throughput and low-latency issues are addressed with modified single-phase decoding schedules. A new "memory-aware" schedule is proposed requiring down to 20% of memory with respect to the traditional two-phase flooding decoding. Additionally, throughput is doubled and logic complexity reduced of 12%. These advantages are traded-off with error correction performance, thus making the solution attractive only for long codes, as those adopted in the DVB-S2 standard. The "layered decoding" principle is extended to those codes not specifically conceived for this technique. Proposed architectures exhibit complexity savings in the order of 40% for both area and power consumption figures, while implementation loss is smaller than 0.05 dB.
Most modern communication standards employ Orthogonal Frequency Division Multiplexing as part of their physical layer. The core of OFDM is the Fast Fourier Transform and its inverse in charge of symbols (de)modulation. Requirements on throughput and energy efficiency call for FFT hardware implementation, while ubiquity of FFT suggests the design of parametric, re-configurable and re-usable IP hardware macrocells. In this context, this thesis describes an FFT/IFFT core compiler particularly suited for implementation of OFDM communication systems. The tool employs an accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results are presented for two deep sub-micron standard-cells libraries (65 and 90 nm) and commercially available FPGA devices. Compared with other FFT core compilers, the proposed environment produces macrocells with lower circuit complexity and same system level performance (throughput, transform size and numerical accuracy).
The final part of this dissertation focuses on the Network-on-Chip design paradigm whose goal is building scalable communication infrastructures connecting hundreds of core. A low-complexity link architecture for mesochronous on-chip communication is discussed. The link enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. The proposed architecture reaches a maximum clock frequency of 1 GHz on 65 nm low-leakage CMOS standard-cells library. In a complex test case with a full-blown NoC infrastructure, the link overhead is only 3% of chip area and 0.5% of leakage power consumption.
Finally, a new methodology, named metacoding, is proposed. Metacoding generates correct-by-construction technology independent RTL codebases for NoC building blocks. The RTL coding phase is abstracted and modeled with an Object Oriented framework, integrated within a commercial tool for IP packaging (Synopsys CoreTools suite). Compared with traditional coding styles based on pre-processor directives, metacoding produces 65% smaller codebases and reduces the configurations to verify up to three orders of magnitude
Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding
No full textReal-time and high-quality video coding is gaining a wide interest in the research and industrial community for different applications. H.264/AVC, a recent standard for high performance video coding, can be successfully exploited in several scenarios including digital video broadcasting, high-definition TV and DVD-based systems, which require to sustain up to tens of Mbits/s. To that purpose this paper proposes optimized architectures for H.264/AVC most critical tasks, Motion estimation and context adaptive binary arithmetic coding. Post synthesis results on sub-micron CMOS standard-cells technologies show that the proposed architectures can actually process in real-time 720 × 480 video sequences at 30 frames/s and grant more than 50 Mbits/s. The achieved circuit complexity and power consumption budgets are suitable for their integration in complex VLSI multimedia systems based either on AHB bus centric on-chip communication system or on novel Network-on-Chip (NoC) infrastructures for MPSoC (Multi-Processor System on Chip
Proceedings - 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008
No full textEuromicro Symposium on Digital System design: Architectures, Methods and Tools (DSD) addresses the
key issues in design, architectures and implementation of digital systems. DSD is a discussion forum for
researchers and engineers working on architectures and implementations of (embedded) digital
systems, as well as efficient design methods and tools.
This year, DSD2008 hosted six Special Sessions, namely Special Session on “Fault Tolerance in Digital
System Design” organized by Zdenek Kotásek, Brno University of Technology (CZ), Special Session on
“Prospective aspects of Networks-on-Chip” organized by Claas Cornelius, University of Rostock (DE),
Special Session on “Dependability and Testing of Digital Systems” organized by Hana Kubátová, Czech
Technical University in Prague (CZ), Special Session on “Planning and Optimization of Sensor Network
Systems” organized by William Fornaciari, Politecnico Milano (IT), Special Session on “System-Level
Energy Optimization of Embedded Software” organized by Eugenio Villar, Universidad de Cantabria (ES)
and Special Session on “NEWCOM++: Flexible Radio Digital Design” organized by Dominique Noguet,
CEA-LETI (FR). I would like to thank the Special Session organizers and their respective program
committees for the time and effort they put in organizing the Special Sessions.
This year, DSD attracted 179 submissions from 37 countries around the world. The increased number of
submissions and wide geographical spread demonstrate the growing popularity of DSD and the
relevance of the topics covered. All submitted works underwent a stringent and blind review process
carried on by at least three independent referees. In some uncertain cases the number of referees was
up to four. Based on the referee reports, the Program Committee selected 46 papers for long
presentation, 46 papers for short presentation and 31 poster presentations.
The three keynote speeches are very topical and are presented by experts from leading semiconductor
and electronic design automation industries. I am sure all participants will enjoy and benefit from the
keynote presentations. A pre-conference Tutorial Day composed of two tutorials entitled: “Qualitydriven
model-based architecture synthesis for real-time embedded SoCs” and “Application mapping on
a composable multi-core NoC-based SoC platform CoMPSoC” are delivered by researchers from NXP
Semiconductors and Eindhoven University of Technology (The Netherlands).
It is a privilege and honor for me to be a chair of the DSD Program Committee. It has been a rewarding
experience. I would like to take this opportunity to thank all of those who worked hard to bring the
programme and the proceedings together. This includes all the Program Committee members and extra
reviewers. I sincerely thank them for their co-operation in the refereeing process. I would like to
express my thanks and gratitude to the Steering Committee members Lech Jozwiak, Antonio Nunez and
Krzysztof Kuchcinski for their constant support and advice. I would like to mention particularly the
unreserved help extended by Prof. Lech Jozwiak.
The symposium could not materialize without the organizing Committee headed by Gianni Conte and
Monica Mordonini (University of Parma) and by Gianni Danese and Francesco Leporati (University of
Pavia). Their hard work will be certainly fruitful to all the participants and will make the stay in Parma
a wonderful experience. My special thanks go to my colleague Sergio Saponara, who assisted me at
every step during the whole year. My thanks and appreciation goes to my Ph.D. Nicola Eugenio
L’Insalata who took care of DSD 2008 web pages.
Last but not least, I would like to thank all the authors for their interest in DSD. Thank you for your
time and effort in preparing and submitting your work to DSD and your patience through the long
process. Your hard work is the backbone of the conference.
I wish you all a pleasant and fruitful meeting in Parma
Slope instability and erosional features of the Ligurian Margin
No full textThe recent conclusion of the Magic Project (Marine Geohazards along the Italian Coasts) (Chiocci & Ridente, 2011), the MALISAR Cruises (Migeon et. Al., 2011; Migeon et al., 2012) and the contribution of the data available at
the Universities of Genoa (IT) and Trieste (IT) allowed us to identify and study the large series of erosional and gravitative phenomena along the Ligurian continental margins. The dataset allowed us to relate the structural
evolution of the Ligurian Basin, the characteristics of the sedimentation, the erosive action of a dense canyon network and the gravitational phenomena (Corradi et al., 2002).
The Ligurian Sea is the northwestern portion of the Mediterranean Sea. It originated from the roto-translation of the Corsica-Sardinia Block and is connected to the Apennine orogenic dynamics (Fanucci & Morelli, 2000). The
complex geological evolution of the Liguran Sea brought to the division of this basin in different physiographic domains. The main one is the Valley of Genoa that separates the margin of the Alpine area from the Apennines one,
which developped in a portion of the newly formed chain. The evolution of the two margins, mainly controlled by extensional tectonics processes, was interrupted by compressional and/or transpressive reactivations, which gave
particular characteristics to the margins (Fanucci & Morelli, 2013; Sage et al., 2013; Sage et al., 2014).
The Alpine margin is characterized by high seismicity, high sedimention rate and steepness of the margin, determining massive and unstable sedimentary masses along the slope, which are carved by a dense network of
canyons.
It is in the western Liguria sector that these erosive features are extensively represented until the "Dorsal of Imperia", a structural element that runs parallel to the margin for about 50-60 kilometers. Its genesis can be attributed to
the effects of a compressive deformation and this structure isolated an intra-slope basin in which huge quantities of sediments were accumulated and drained by canyons and conveyed in the Valley of Genoa, through the
Canyon of Vado.
The continental margin between the City of Genoa and the Portofino Promontory is characterized by the two main canyons of the Ligurian Gulf: the Polcevera and the Bisagno canyons. These are in continuity with their
respective rivers and almost entirely eroded a thick Plio-Quaternary sequence.
The Apennine margin presents a less complex structure than the Alpine one (Fanucci & Morelli, 2006); however, large gravitative phenomena are present. The most important is the Portofino Landslide, located in front of the
corresponding promontory. It is mainly characterized by rotational slips and incipient detachment niches, stimulated by the erosion at the base by the Levante Canyon. This last, oriented along the Apennine tectonic lineations,
produces significant erosion, both on the head than along its way, which is almost parallel to the coast until its confluence in the Bisagno Canyon.
References
Chiocci F.L. & Ridente D. 2011. Regional-scale seafloor mapping and geohazard assessment. The experience from the Italian project MaGIC (Marine Geohazards along the Italian Coasts). Mar. Geophys. Res., 32 (1-2),
13-23.
Corradi N., Cuppari A., Fanucci F. & Morelli D. 2002. Gravitative instability of sedimentary masses on the Ligurian Sea margins. GeoActa, 1, 37-44.
Fanucci F.,& Morelli D. 2000. Caratteri e cronologia della deriva del Blocco Sardo-Corso. Atti Ass. It. Oceanol. Limnol., 13 (2), 167-181
Fanucci F.,& Morelli D. 2006. Assetto strutturale ed evoluzione polifasica del Margine appenninico tra Portofino e La Spezia. Rend. Soc. Geol. It., http://hdl.handle.net/11368/1693875
Fanucci F.,& Morelli D. 2013. Rapporti tra morfologia e tettonica sul margine continentale ligure. http://hdl.handle.net/11368/2768328
Migeon S., Cattaneo A., Hassoun V., Larroque C., Corradi N., Fanucci F., Dano A., Mercier de Lepinay B., Sage F. & Gorini C. 2011. Morphology, distribution and origin of recent submarine landslides of the Ligurian
Margin (North-western Mediterranean): some insights into geohazard assessment. Mar. Geophys. Res., 32 (1-2), 225-243.
Migeon S., Cattaneo A., Hassoun V., Dano A., Casedevant A. & Ruellan E. (2012). Failure Processes and Gravity-Flow Transformation Revealed by High-Resolution AUV Swath Bathymetry on the Nice Continental Slope
(Ligurian Sea). Advances in Natural and Technological Hazards Research, 31, 451-461.
Sage F., Beslier M.O., Gaullier V., Larroque L., Dessa J.X., Mercier de Lepinay B., Corradi N., Migeon S., Katz H., & Ruiz Constan A. 2013. Partitioning of deformation along a reactivated rifted margin:example of the northern
Ligurian margin. Geophys. Res. Abs. Vol. 15. http://hdl.handle.net/11567/692573.
Sage F., Beslier M.O., Dessa J.X., Schénini L., Watremez L., Mercier de Lépinay B., Gaullier V., Larroque C., Béthoux N., Corradi N., Bigot A., Migeon S., & Ruiz Constan A. 2014. Inversion of back-arc basins: example of the
LigurianBasin, Western Mediterranean. Geophys. Res. Abs. Vol. 16, EGU2014¬15668, http://hdl.handle.net/11567/692574
Front-end Electronics for GEM detectors
No full textThe work presented in this thesis is focused on the design of a 32 channel CMOS front-end ASIC intended for the read-out of GEM detectors to be used in a new proton-therapy facility for beam monitoring. Each single analog channel, based on the classic architecture CSA + shaper, is able to sample the energy of the incoming event by means of a peak detector (PD) which works as an analog memory during the read-out phase. In order to have energy information directly in digital form, the ASIC is equipped with an integrated 8-bit subranging ADC, so the outputs of the PDs are multiplexed towards the A/D conversion path. The outputs of 32 voltage discriminators, which compare the shaper outputs with a programmable threshold, produce an accurate and fast trigger signal which identifies with good time resolution the occurrence of a valid event. The read-out of the channels, the A/D conversion and the configuration of the ASIC are managed by a digital part which also carries out data serialization on a 100 Mbit/s LVDS serial link. Measured results are presented, showing the full functionality of the ASIC and the performance of the analog channel in good agreement with the given specification
Configurable network-on-chip router macrocells
No full textThis paper presents a configurable architecture for Network-on-Chip (NoC) router macrocells, and a methodology to streamline their design and configuration. The methodology addresses the typical problems experienced by design and verification engineers when coding highly configurable intellectual property macrocells at Register Transfer Level (RTL) with hundreds of parameters and thousands of resulting configurations. A NoC infrastructure for a Multi Processor System-on-Chip (MPSoC) may require tens or hundreds of router macrocells. Therefore, managing the configuration design space is becoming a bottleneck for the design and verification of many-core processing systems. The proposed generation flow is illustrated on a real-world NoC router core. Its configurable architecture is compliant with several NoC topologies such as Ring, Octagon, Spidergon and 2D mesh typically used in many-core processing platforms. The generation flow allows for a reduction in the database code size, up to 70% in our experiments, and a contraction of three orders of magnitudes of the verification space vs. conventional design flows of RTL macrocells. The validity of the approach is also confirmed by synthesizing the generated router macrocells in nanoscale CMOS technology. The achieved performance compare well to the state-of-the-art in terms of low latency and low circuit complexit
Design and Preliminary Validation of an Assisted Driving System for Obstacle Avoidance Based on Reinforcement Learning Applied to Electrified Wheelchairs
No full textOperating a motorized wheelchair poses inherent risks and demands substantial cognitive effort to achieve effective environmental awareness. Consequently, individuals with severe disabilities face heightened risk, leading to diminished social engagement which impacts their overall well-being. Therefore, we have developed a collaborative driving system for obstacle avoidance based on a trained reinforcement learning (RL) algorithm. The system interfaces with the user through a joystick, capturing the desired direction and speed, while a lidar positioned in front of the wheelchair provides information about obstacle distribution. Taking both inputs into account, the system generates a pair of forward and rotational speeds that prioritize obstacle avoidance while closely aligning with the user’s commands. Preliminary validation through simulations involved comparing the RL algorithm with the absence of an assistive system. The results are promising, showcasing that the RL algorithm reduces collisions without imposing constraints on the desired speed. Ongoing research is dedicated to expanding tests and conducting comparisons with traditional obstacle avoidance algorithms
Grief: Finding Hope in Sorrow
No full textLoss comes to each of us, without fail. Scripture can serve as a companion to us in the grief we bear and ultimately in our surrender to our compassionate God. Through this set of insightful reflections on the stories of Ruth and Naomi, the death and raising of Jesus\u27 friend Lazarus, and the promise of a new heaven and earth, Laura Kelly Fanucci invites us to a deepening experience of God\u27s healing presence in our lives.
Laura Kelly Fanucci is the research associate for the Collegeville Institute Seminars. She is the author of Mercy: God\u27s Nature, Our Challenge and Dashed Hopes: When Our Best-Laid Plans Fall Apart in the Alive in the Word series; Everyday Sacrament: The Messy Grace of Parenting (Liturgical Press, 2014); and the coauthor of Living Your Discipleship: 7 Ways to Express Your Deepest Calling (23rd Publications, 2015). She blogs about spirituality and parenting at www.motheringspirit.comhttps://digitalcommons.csbsju.edu/collegevilleinstitute_books/1002/thumbnail.jp
Data-Driven Convolutional Model for Digital Color Image Demosaicing
No full textModern digital cameras use specific arrangement of Color Filter Array to sample light wavelength corresponding to visible colors. The most common Color Filter Array is the Bayer filter that samples only one color per pixel. To recover the full resolution image, an interpolation algorithm can be used. This process is called demosaicing and it is one of the first processing stages of a digital imaging pipeline. We introduce a novel data-driven model for demosaicing that takes into account the different requirements for reconstruction of the image Luma and Chrominance channels. The final model is a parallel composition of two reconstruction networks with individual architecture and trained with distinct loss functions. In order to solve the overfitting problem, we prepared a dataset that contains groups of patches that share common chromatic and spectral characteristics. We reported the reconstruction error on noise-free images and measured the effect of random noise and quantization noise in the demosaicing reconstruction. To test our model performance, we implemented the network on NVIDIA Jetson Nano, obtaining an end-to-end running time of less than one second for a full frame 12 MPixel image
A Parallel VLSI Architecture for 1-Gb/s, 2048-b, Rate-1/2 Turbo Gallager Code Decoder
No full textThis paper presents a 2048 bit, rate 1/2 soft decision decoder for a new class of codes known as Turbo Gallager Codes. The decoder can support up to 1 Gbit/s code rate and performs up to 48 decoding iteration ensuring at the same time high throughput and good coding gain. In order to evaluate the performance and the gate complexity of the decoder VLSI architecture, it has been synthesized in a 0.18 μm standard-cell CMOS technology
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