55 research outputs found
Leakage Models for High Level Power Estimation
No full textIn heutigen sub-100nm CMOS Systemen sind Leckströme von hoher Bedeutung. Diese können auf Transistorebene langsam aber genau (BSIM oder PSP) und auf der Gatter-Ebene schneller aber unter Vernachlässigung wichtiger Parameter (Liberty) vorhergesagt werden. In dieser Arbeit werden Modelle auf RT Ebene entwickelt, die schneller als bisherige Gatter Modelle aber nahezu so genau wie Transistormodelle sind. Dafür wird eine Modellhierarchie von einfachen Transistorbeschreibungen über Gattermodelle bis hin zu RT Soft Makros entwickelt, in der alle wesentlichen Parameter entweder zur nächsten Ebene durchgereicht (und sind dann bis hin zur Systemebene verfügbar) oder, wo möglich, implizit in die Modelle integriert werden. Diese Modelle sind millionenfach schneller als SPICE aber innerhalb von 3.6% - 6.9% Standardabweichung für eine weite Spanne an Temperaturen, Betriebsspannungen und Prozessvariationen
Accelerating and Pruning CNNs for Semantic Segmentation on FPGA
No full textSemantic segmentation is one of the popular tasks in computer
vision, providing pixel-wise annotations for scene understanding. However, segmentation-based convolutional neural networks
require tremendous computational power. In this work, a fully-pipelined hardware accelerator with support for dilated convolution is introduced, which cuts down the redundant zero multiplications. Furthermore, we propose a genetic algorithm based
automated channel pruning technique to jointly optimize computational complexity and model accuracy. Finally, hardware heuristics
and an accurate model of the custom accelerator design enable
a hardware-aware pruning framework. We achieve 2.44× lower
latency with minimal degradation in semantic prediction quality
(−1.98 pp lower mean intersection over union) compared to the
baseline DeepLabV3+ model, evaluated on an Arria-10 FPGA
Logic design techniques for 65 to 45nm and below for reducing total energy and solving technology variations problems
No full textLow Power and High-Throughput LUT-based Accelerator Architecture for Distributed CNN Inference at the Edge
No full textEnabling distributed CNN inference at network's edge demands efficient solutions due to resource limitations and strict timing and energy constraints. LUT-based architectures, which aims at storing pre-computed neural network layers as LUTs, allow eliminating external memory and enabling fast, energy-efficient inference. Their use into an ecosystem for distributed CNN processing across multiple edge devices opens the door to novel applications in the field of future mobility and aerospace. In this paper, we present a flow using LUT-based accelerators for distributed CNN inference at edge
Using Network Architecture Search for Optimizing Tensor Compression
No full textIn this work we propose to use Network Architecture Search
(NAS) for controlling the per layer parameters of a Tensor Compression
(TC) algorithm using Tucker decomposition in order to optimize a given
convolutional neural network for its parameter count and thus inference
performance on embedded systems. TC enables a quick generation of the
next instance in the NAS process, avoiding the need for a time consuming
full training after each step. We show that this approach is more effcient
than conventional NAS and can outperform all TC heuristics reported
so far. Nevertheless it is still a very time consuming process, ending a
good solution in the vast search space of layer-wise TC. We show that,
it is possible to reduce the parameter size upto 85% for the cost of 0.1-
1% of Top-1 accuracy on our vision processing benchmarks. Further,
it is shown that the compressed model occupies just 20% of the original
memory size which is required for storing the entire uncompressed model,
with an increase in the inference speed of upto 2.5 times without much
loss in the performance indicating potential gains for embedded systems
Modular Over‐the‐air Software Updates for Safety‐critical Real‐time Systems
No full textAutomotive software is undergoing a rapid change toward artificial intelligence and towards more and more connectedness with other systems. For both, an incremental design paradigm is desired, where the car's software is frequently updated after production but still can guarantee the highest automotive safety standards. We present a design flow and tool framework enabling a DevOps paradigm for automotive software development. DevOps means that software is developed in a continuous loop of development, deployment, usage in the field, collection of runtime data and feedback to the developers for the next design iteration. The software developers get support in defining, developing, and verifying new software functions based on the data gathered in the field by the previous software generation. The software developers can define contracts describing the time and resource assumptions on the integration environment and guarantees for other dependent software components in the system. These contracts allow a composition of software components and proof obligations to be discharged at design time through virtual integration testing and runtime through continuous monitoring of assumptions and guarantees on the software component's interfaces. An update package, consisting of the software component and its contracts, is then automatically created, transferred over the air, and deployed in the car. Monitors derived from the contracts allow for supervising the system's behavior, detecting failures at runtime, and annotating the situation to be included in a data collection, fueling the next design iteration
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