1,721,078 research outputs found
Low-Complexity Architectures of a Decoder for IEEE 802.16e LDPC Codes
No full textLow-density parity-check (LDPC) codes have recently been included as error-correcting codes in IEEE 802.16e, for wireless metropolitan area networks. This paper proposes a flexible, low-complexity LDPC decoder fully compliant with all 114 codes defined by the standard. The decoder runs the layered decoding algorithm to increase the convergence speed, and relies on a semi-parallel implementation with serial processing units working in pipeline to reduce the latency. Particularly, two different architectures are considered, and their RTL/memory complexity tradeoffs are analyzed. The resulting design yields a throughput ranging from 93 to 497 Mbps by means of 15 iterations at the clock frequency of 400 MHz. Synthesis on 65 nm CMOS technology, shows a chip area less than 0.59 mm2, despite the high flexibility, which compares favourably with similar implementations
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
La cornice legislativa: i contratti di riallineamento, la legge n. 383 del 2001, la riforma dei servizi ispettivi
No full text
A Minimum-Latency Block-Serial Architecture of a Decoder for IEEE 802.11n LDPC Codes
No full textThis paper describes a scalable architecture of a decoder for IEEE 802.11n low-density parity-check (LDPC) codes. The decoder runs the layered decoding algorithm and its architecture is arranged in clusters of serial functional units, which are configured to process all codes in the standard. The decoder works in pipeline, and a very effective technique to rearrange the sequence of its elaborations is proposed in order to minimize the iteration latency; this relates to the order of the messages input and output by the processing units, as well as the sequence of layers followed for decoding. Moreover, memory optimization techniques have been applied to get a very efficient partitioning, allowing the pipeline of the operations. The synthesis on 65 nm CMOS technology with low-power standard-cell library, shows that the proposed design is suitable for portable devices, the throughput ranging from 136 to 355 Mbps, and the power consumption being below 185mW
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