3,563 research outputs found
An Exploration And Modernization Of Classical Existential Thought Through Fiction
No full textAuthor Chip Fankhauser explores classical existential philosophy through a series of fictional short stories. Each story deals with a different subject matter and theme of classical existentialism. In this collection Fankhauser also experiments with form and technique in an effort to develop more as a writer
High-resolution and multi-range particle separation by microscopic vibration in an optofluidic chip
No full textAn optofluidic chip is demonstrated in experiments for high-resolution and multi-range particle separation through the optically-induced microscopic vibration effect, where nanoparticles are trapped in loosely overdamped optical potential wells created with combined optical and fluidic constraints. It is the first demonstration of separating single nanoparticles with diameters ranging from 60 to 100 nm with a resolution of 10 nm. Nanoparticles vibrate with an amplitude of 3-7 mu m in the loosely overdamped potential wells in the microchannel. The proposed optofluidic device is capable of high-resolution particle separation at both nanoscale and microscale without reconfiguring the device. The separation of bacteria from other larger cells is accomplished using the same chip and operation conditions. The unique trapping mechanism and the superb performance in high-resolution and multi-range particle separation of the proposed optofluidic chip promise great potential for a diverse range of biomedical applications.Singapore National Research Foundation under the Competitive Research Program [NRF-CRP13-2014-01]; Singapore National Research Foundation under Incentive for Research & Innovation Scheme [1102-IRIS-05-02]SCI(E)ARTICLE142443-24501
A fully sealed plastic chip for multiplex PCR and its application in bacteria identification
No full textMultiplex PCR is an effective tool for simultaneous multiple target detection but is limited by the intrinsic interference and competition among primer pairs when it is performed in one reaction tube. Dividing a multiplex PCR into many single PCRs is a simple strategy to overcome this issue. Here, we constructed a plastic, easy-to-use, fully sealed multiplex PCR chip based on reversible centrifugation for the simultaneous detection of 63 target DNA sequences. The structure of the chip is quite simple, which contains sine-shaped infusing channels and a number of reaction chambers connecting to one side of these channels. Primer pairs for multiplex PCR were sequentially preloaded in the different reaction chambers, and the chip was enclosed with PCR-compatible adhesive tape. For usage, the PCR master mix containing a DNA template is pipetted into the infusing channels and centrifuged into the reaction chambers, leaving the infusing channels filled with air to avoid cross-contamination of the different chambers. Then, the chip is sealed and placed on a flat thermal cycler for PCR. Finally, amplification products can be detected in situ using a fluorescence scanner or recovered by reverse centrifugation for further analyses. Therefore, our chip possesses two functions: 1) it can be used for multi-target detection based on end-point in situ fluorescence detection; and 2) it can work as a sample preparation unit for analyses that need multiplex PCR such as hybridization and target sequencing. The performance of this chip was carefully examined and further illustrated in the identification of 8 pathogenic bacterial genomic DNA samples and 13 drug-resistance genes. Due to simplicity of its structure and operation, accuracy and generality, high-throughput capacity, and versatile functions (i.e., for in situ detection and sample preparation), our multiplex PCR chip has great potential in clinical diagnostics and nucleic acid-based point-of-care testing.National Hi-Tech Program of China [2012AA020101]; China Postdoctoral Science Foundation [2012 M510464]; National Natural Science Foundation of China [81327005, 81471749]; National Sci-Tech Support Plan [2012EP001002]; Beijing lab foundationSCI(E)[email protected]
System-on-chip Computing and Interconnection Architectures for Telecommunications and Signal Processing
No full textThis dissertation proposes novel architectures and design techniques targeting SoC building blocks for telecommunications and signal processing applications.
Hardware implementation of Low-Density Parity-Check decoders is approached at both the algorithmic and the architecture level. Low-Density Parity-Check codes are a promising coding scheme for future communication standards due to their outstanding error correction performance.
This work proposes a methodology for analyzing effects of finite precision arithmetic on error correction performance and hardware complexity. The methodology is throughout employed for co-designing the decoder. First, a low-complexity check node based on the P-output decoding principle is designed and characterized on a CMOS standard-cells library. Results demonstrate implementation loss below 0.2 dB down to BER of 10^{-8} and a saving in complexity up to 59% with respect to other works in recent literature. High-throughput and low-latency issues are addressed with modified single-phase decoding schedules. A new "memory-aware" schedule is proposed requiring down to 20% of memory with respect to the traditional two-phase flooding decoding. Additionally, throughput is doubled and logic complexity reduced of 12%. These advantages are traded-off with error correction performance, thus making the solution attractive only for long codes, as those adopted in the DVB-S2 standard. The "layered decoding" principle is extended to those codes not specifically conceived for this technique. Proposed architectures exhibit complexity savings in the order of 40% for both area and power consumption figures, while implementation loss is smaller than 0.05 dB.
Most modern communication standards employ Orthogonal Frequency Division Multiplexing as part of their physical layer. The core of OFDM is the Fast Fourier Transform and its inverse in charge of symbols (de)modulation. Requirements on throughput and energy efficiency call for FFT hardware implementation, while ubiquity of FFT suggests the design of parametric, re-configurable and re-usable IP hardware macrocells. In this context, this thesis describes an FFT/IFFT core compiler particularly suited for implementation of OFDM communication systems. The tool employs an accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results are presented for two deep sub-micron standard-cells libraries (65 and 90 nm) and commercially available FPGA devices. Compared with other FFT core compilers, the proposed environment produces macrocells with lower circuit complexity and same system level performance (throughput, transform size and numerical accuracy).
The final part of this dissertation focuses on the Network-on-Chip design paradigm whose goal is building scalable communication infrastructures connecting hundreds of core. A low-complexity link architecture for mesochronous on-chip communication is discussed. The link enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. The proposed architecture reaches a maximum clock frequency of 1 GHz on 65 nm low-leakage CMOS standard-cells library. In a complex test case with a full-blown NoC infrastructure, the link overhead is only 3% of chip area and 0.5% of leakage power consumption.
Finally, a new methodology, named metacoding, is proposed. Metacoding generates correct-by-construction technology independent RTL codebases for NoC building blocks. The RTL coding phase is abstracted and modeled with an Object Oriented framework, integrated within a commercial tool for IP packaging (Synopsys CoreTools suite). Compared with traditional coding styles based on pre-processor directives, metacoding produces 65% smaller codebases and reduces the configurations to verify up to three orders of magnitude
Mimicking liver sinusoidal structures and functions using a 3D-configured microfluidic chip
No full textPhysiologically four major types of hepatic cells - the liver sinusoidal endothelial cells Kupffer cells hepatic stellate cells and hepatocytes - reside inside liver sinusoids and interact with flowing peripheral cells under blood flow. It is hard to mimic an in vivo liver sinusoid due to its complex multiple cell-cell interactions spatiotemporal construction and mechanical microenvironment. Here we developed an in vitro liver sinusoid chip by integrating the four types of primary murine hepatic cells into two adjacent fluid channels separated by a porous permeable membrane replicating liver's key structures and configurations. Each type of cells was identified with its respective markers and the assembled chip presented the liver-specific unique morphology of fenestration. The flow field in the liver chip was quantitatively analyzed by computational fluid dynamics simulations and particle tracking visualization tests. Intriguingly co-culture and shear flow enhance albumin secretion independently or cooperatively while shear flow alone enhances HGF production and CYP450 metabolism. Under lipopolysaccharide (LPS) stimulations the hepatic cell co-culture facilitated neutrophil recruitment in the liver chip. Thus this 3D-configured in vitro liver chip integrates the two key factors of shear flow and the four types of primary hepatic cells to replicate key structures hepatic functions and primary immune responses and provides a new in vitro model to investigate the short-duration hepatic cellular interactions under a microenvironment mimicking the physiology of a liver
High-voltage capacitively coupled contactless conductivity detection for conventional and microchip capillary electrophoresis
No full textThis thesis focuses on the optimisation of capacitively coupled contactless conductivity detection for capillary and microchip electrophoresis and its applications in analytical chemistry. First, the effect of high excitation voltages and operation frequencies on the capacitively coupled contactless conductivity detector cell for conventional capillary electrophoresis is evaluated. The detector electrodes comprised two steel tubes cut from hypodermic needles, through which the capillaries were inserted. It is demonstrated that increasing excitation voltages from 25 V pp, to 250 Vpp improves the detection limits by a factor of 10. The high actuator voltage approach was also investigated for contactless conductivity detection on a glass-microchip device with ancm long channel. The detector electrodes formed part of the microchip and were placed on the microchip directly above the microchannel. In a separate project the simplification of on-microchip contactless conductivity detection was accomplished. This was achieved by integrating the detector electrodes on to a chip-holder specifically designed for this purpose. Thus the electrodes were a part of the holder, an improvement of the previous arrangement whereby the detector electrodes were situated on the microdevice. Finally the applications and advantages of the optimised high-voltage capacitively coupled contactless conductivity detection for inorganic and organic analysis were demonstrated. The separation and detection of 14 metal ions was accomplished in less than six minutes. The compatibility of this detector with non-UV transparent, polymer capillaries has been demonstrated. The detection of native amino acids has been evaluated. Part of the work was dedicated to the on-chip analysis of various classes of organic ions. The two immunoproteins human immunoglobulin M (IgM) and immunoglobulin G (IgG), were analysed in their unlabelled state on both capillary and lab-on-chip platforms. All species involved in an immunological interaction between IgM and IgG could be detected. A method for the analysis of selected basic pharmaceutical drug substances was developed. Detection limits comparable to those supplied by direct UV detection were obtained. Main component assays of selected pharmaceutical preparations have been demonstrated
Polymer multimode waveguide optical and electronic PCB manufacturing
No full textThe paper describes the research in the £1.3 million IeMRC Integrated Optical and Electronic Interconnect PCB Manufacturing (OPCB) Flagship Project in which 8 companies and 3 universities carry out collaborative research and which was formed and is technically led by the author. The consortium’s research is aimed at investigating a range of fabrication techniques, some established and some novel, for fabricating polymer multimode waveguides from several polymers, some formulations of which are being developed within the project. The challenge is to develop low cost waveguide manufacturing techniques compatible with commercial PCB manufacturing and to reduce their alignment cost. The project aims to take the first steps in making this hybrid optical waveguide and electrical copper track printed circuit board disruptive technology widely available by establishing and incorporating waveguide design rules into commercial PCB layout software and transferring the technology for fabricating such boards to a commercial PCB manufacturer. To focus the research the project is designing an optical waveguide backplane to tight realistic constraints, using commercial layout software with the new optical design rules, for a demonstrator into which 4 daughter cards are plugged, each carrying an aggregate of 80 Gb/s data so that each waveguide carries 10 Gb/s
Chip-Firing Revisited: A Peek into the Third Dimension
No full textChip-firing was first introduced as a probabilistic game. Subsequently, it was generalized to arbitrary graph configurations and investigated mostly with regard to two-dimensional quad-grid layouts. In this paper, we lift chip-firing to the third dimension. Aside from the arising three-dimensional shapes, we are interested in the internal, two-dimensional structures. Furthermore, we explore the different shapes obtained by chip firing processes on various neighborhoods, such as the face-centered and the cube-centered grid as well as on a neighborhood inspired by knight moves.Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Computer Graphics and Visualisatio
Synthetic life on a chip
No full textIn this article, we argue that on-chip microfluidic systems provide an attractive technology when it comes to designing synthetic cells. We emphasize the importance of the surrounding environment for both living systems in nature and for developing artificial self-sustaining entities. On-chip microfluidic devices provide a high degree of control over the production of cell-like synthetic entities as well as over the local microenvironment that these soft-matter-based synthetic cells experience. Rapid progress in microfluidic fabrication technology has led to a variety of production and manipulation tools that establish on-chip environments as a versatile platform and arguably the best route forward for realizing synthetic life.Accepted Author ManuscriptBN/Cees Dekker La
2-D and 3-D Integration of Heterogeneous Electronic Systems under Cost, Performance and Technological Constraints
No full textAbstract—Present day market demand for high-performance high-density portable hand-held applications has shifted the focus from 2-D planar system-on-a-chip-type single-chip solutions to al-ternatives such as tiled silicon and single-level embedded modules as well as 3-D die stacks. Among the various choices, finding an optimal solution for system implementation deals usually with cost, performance, power, thermal, and technological tradeoff analyses at the system conceptual level. It has been estimated that decisions made in the first 20 % of the design cycle influence up to 80 % of the final product cost. In this paper, we discuss realistic metrics appropriate for performance and cost tradeoff analyses both at the system conceptual level in the early stages of the design cycle and in the implementation phase, for verification. In order to validate the proposed metrics and methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and the performance tradeoffs discussed. This case study is used to highlight the importance of a cost and performance tradeoff analysis early in the design flow. Index Terms—Die stacking, performance and cost tradeoffs, power consumption, system-in-package (SiP), system-on-chip (SoC), system-on-package (SoP), thermal analysis, wafer-level integration (WLI), 3-D integration. I
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