242 research outputs found
The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms
No full textDataflow specifications are suitable to describe both signal processing applications and the relative specialized hardware architectures, fostering the hardware–software development gap closure. They can be exploited for the development of automatic tools aimed at the integration of multiple applications on the same coarse-grained computational substrate. In this paper, the multi-dataflow composer (MDC) tool, a novel automatic platform builder exploiting dataflow specifications for the creation of run-time reconfigurable multi-application systems, is presented and evaluated. In order to prove the effectiveness of the adopted approach, a coprocessor for still image and video processing acceleration has been assembled and implemented on both FPGA and 90 nm ASIC technology. 60 % of savings for both area occupancy and power consumption can be achieved with the MDC generated coprocessor compared to an equivalent non-reconfigurable design, without performance losses. Thanks to the generality of high-level dataflow specification approach, this tool can be successfully applied in different application domains
A custom MPSoC architecture with integrated power management for real-time neural signal decoding
No full textBioengineering research is posing hard challenges to digital embedded system designers. Tight real-time constraints, miniaturization, and low power are critical issues exacerbated by applications requiring the implant of electronic devices in the patient's body. Among them, neurocontrolled motor prostheses are on the cutting edge of the research in the field, requiring the real-time neural signal decoding to extract the patient's movement intention in order to control the mechatronic device. Despite the literature in the field, how to implement a highly-portable and reliable integrated platform is still an open question. In this paper, we propose a field-programmable gate array-based prototype of an multi-processor system-on-chip embedded architecture that implements an online neural signal decoding algorithm. The prototype is capable of respecting the real-time constraints posed by the application when clocked at less than 50 MHz. Considering that the application workload is extremely data dependent and unpredictable, the architecture has to be dimensioned taking into account critical worst-case operating conditions to ensure robustness. To compensate the resulting over-provisioning of the system architecture, a software-controllable power management has been integrated. Experimental results demonstrate the real-time behavior and allow evaluating the usefulness of the proposed power management technique on public databases
Exploring custom heterogeneous MPSoCs for real-time neural signal decoding
No full textThe design of embedded systems for neuroprosthetic applications represents an important challenge to be faced in electronic bioengineering. One of the key research problems is decoding the information encoded in neural signals to extract the patient's motion intention. How to implement a highly-portable and reliable integrated solution is still an open issue. In this paper, we investigate the possibility of adopting the MPSoC paradigm in this application domain, presenting a design space exploration that evaluates different custom MPSoC embedded architectures, implementing an on-line neural signal decoding algorithm. The evaluated design points feature different mappings of parallel software tasks onto customized ASIP processing cores. Experimental results, obtained by FPGA-based prototyping, assess the performance and hardware-related costs of the considered configurations. The clock frequency needed to respect real-time constraints was reduced to 22 MHz, making a step further towards the exploitation of custom heterogeneous MPSoCs for ultra-low power biomedical signal processing
Checking Flavour Models at Neutrino Facilities
No full textAbstractIn the recent years, the industry of model building has been the subject of the intense activity, especially after the measurement of a relatively large values of the reactor angle. Special attention has been devoted to the use of non-abelian discrete symmetries, thanks to their ability of reproducing some of the relevant features of the neutrino mixing matrix. In this Letter, we consider two special relations between the leptonic mixing angles, arising from models based on S4 and A4, and study whether, and to which extent, they can be distinguished at superbeam facilities, namely T2K, NOνA and T2HK
Superior responsibility for acts of torture committed by subordinates under international criminal law. The case of U.S. abuse against iraqi prisoners
No full textThe paper deals with the abuse and tortures committed at Abu Ghraib by american soldiers on Iraqi prisoners that have become ‘famous’ worldwide, being documented by a large number of photos taken by the same soldiers actually
involved in the torture practices. The repeated and systematic occurrence of acts of abuse against detainees in Iraq (or in other places, as Afghanistan) implies some legal questions regarding the criminal accountability of the subjects involved, from the ordinary soldier, direct perpetrator of the offences, up along the chain of command. More specifically, declarations such
as Colonel T. admission that he knew his soldiers used the ‘claustrophobic technique’, and was therefore aware of the physical abuse that occurred but did not intervene to stop them, raise substantial questions that need to be addressed. No doubt a soldier who intentionally commits torture is responsible for his actions, but what about the officer that ordered, approved or failed to intervene when he knew that torture was occurring? the author argues that the unlawful interrogation techniques used by U.S. military personnel in Iraq and Afghanistan should be viewed as the result of decisions taken at the highest levels, and of failure to prevent and punish such crimes. Therefore responsibility should be attributed accordingli to the higher echelons, also at the political level, along with the actual perpetrators of the criminal acts
An FPGA Platform for Real-Time Simulation of Spiking Neuronal Networks
No full textIn the last years, the idea to dynamically interface biological neurons with artificial ones has become more and more urgent. The reason is essentially due to the design of innovative neuroprostheses where biological cell assemblies of the brain can be substituted by artificial ones. For closed-loop experiments with biological neuronal networks interfaced with in silico modeled networks, several technological challenges need to be faced, from the low-level interfacing between the living tissue and the computational model to the implementation of the latter in a suitable form for real-time processing. Field programmable gate arrays (FPGAs) can improve flexibility when simple neuronal models are required, obtaining good accuracy, real-time performance, and the possibility to create a hybrid system without any custom hardware, just programming the hardware to achieve the required functionality. In this paper, this possibility is explored presenting a modular and efficient FPGA design of an in silico spiking neural network exploiting the Izhikevich model. The proposed system, prototypically implemented on a Xilinx Virtex 6 device, is able to simulate a fully connected network counting up to 1,440 neurons, in real-time, at a sampling rate of 10 kHz, which is reasonable for small to medium scale extra-cellular closed-loop experiments
Correction to: Thinking embodiment with genetics: epigenetics and postgenomic biology in embodied cognition and enactivism (Synthese, (2020), 10.1007/s11229-020-02748-3)
No full textThe article Thinking embodiment with genetics: epigenetics and postgenomic biology in embodied cognition and enactivism, written by Maurizio Meloni and Jack Reynolds, was originally published electronically on the publisher’s internet portal on 18 June 2020 without open access. With the author(s)’ decision to opt for Open Choice the copyright of the article changed on 6 November 2020 to ©The Author(s) 2020 and the article is forthwith distributed under a Creative Commons Attribution
Percepire e rappresentare lo spazio oltre la visione. Strategie di comunicazione multisensoriale per l’accessibilità del Museo di Arte Orientale Edoardo Chiossone
No full textHow does a blind person perceive architectural space? This text explores the relationship between body, perception and architecture, analizing how sighted and blind people understand and mentally reconstruct space. At the centre of the research is the Edoardo Chiossone Museum of Oriental Art in Genoa, designed by Mario Labò and the subject, over time, of reflections on accessibility, including the project – never built – by Gae Aulenti, conceived to expand the building and improve its usability, without affecting its architectural value. Through an investigation that intertwines perception, representation and wayfinding, the author addresses the expressive potential of multisensoriality and proposes an idea of accessibility that goes beyond the removal of physical barriers. The history and complex path of the museum become the terrain for experiments conducted in collaboration with the Italian Union of the Blind and Partially Sighted, opening up new ways of exploring and understanding space. Digital technologies such as panoramic photography and virtual tours are integrated with the bodily experience of a real visit, supported by physical tools that activate touch and hearing, promoting a deeper understanding of architecture. A new range of tools emerges for a truly inclusive museum experience. The result is a current and necessary reflection on the design of architectural space, understood as a sensitive experience, accessible and shared by all.PublishedCome percepisce lo spazio architettonico una persona cieca? Questo testo esplora il rapporto tra corpo, percezione e architettura, analizzando come vedenti e non vedenti comprendano e ricostruiscano mentalmente lo spazio. Al centro della ricerca vi è il Museo di Arte Orientale Edoardo Chiossone di Genova, progettato da Mario Labò e oggetto, nel tempo, di riflessioni sull’accessibilità, tra cui il progetto – mai realizzato – di Gae Aulenti, pensato per ampliare l’edificio e migliorarne la fruibilità, senza intaccarne il valore architettonico. Attraverso un’indagine che intreccia percezione, rappresentazione e wayfinding, l’autore affronta le potenzialità espressive della multisensorialità e propone un’idea di accessibilità che va oltre la rimozione delle barriere fisiche. La storia e la complessa percorrenza del museo diventano terreno per sperimentazioni condotte in collaborazione con l’Unione Italiana Ciechi e Ipovedenti, aprendo a nuove modalità di esplorazione e comprensione dello spazio. Tecnologie digitali come la fotografia panoramica e i virtual tour si integrano con l’esperienza corporea della visita reale, supportata da strumenti fisici che attivano il tatto e l’udito, favorendo una comprensione più profonda dell’architettura. Ne emerge una nuova gamma di strumenti per una fruizione museale realmente inclusiva. Il risultato è una riflessione attuale e necessaria sul progetto dello spazio architettonico, inteso come esperienza sensibile, accessibile e condivisa da tutti
MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation
No full textIn this paper we target the design of a dedicated low-power computing platform for neuroprosthetic applications. The system must be capable of decoding the information encoded in neural signals, to extract the patients’ motion intention. To this aim, a highly-portable and reliable integrated processing device is required. However, a commonly acknowledged design methodology, to be used in such kind of design cases, is still not available in literature. In this work, we propose and assess the adoption of the MPSoC paradigm as a prospective solution. We present a design-case of a custom MPSoC integrated solution, implementing an on-line neural signal decoding algorithm. The proposed system executes parallel software tasks onto customized ASIP processing cores. Experimental results, obtained by placement- and activity-aware power evaluations carried out using an industrial 40 nm technology node as a reference, assess that the performance and power-related features of the designed architecture are compliant with the implantability constraints and with the battery lifetime required for real-life use. Moreover, besides the effectiveness of the proposed solution, this paper demonstrates also that custom heterogeneous MPSoCs can successfully challenge ultra-low power bio-medical signal processing problem
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs
No full textAn important research problem, at the basis of the development of embedded systems for neuroprosthetic applications, is the development of algorithms and platforms able to extract the patient's motion intention by decoding the information encoded in neural signals. At the state of the art, no portable and reliable integrated solutions implementing such a decoding task have been identified. To this aim, in this paper, we investigate the possibility of using the MPSoC paradigm in this application domain. We perform a design space exploration that compares different custom MPSoC embedded architectures, implementing two versions of a on-line neural signal decoding algorithm, respectively targeting decoding of single and multiple acquisition channels. Each considered design points features a different application configuration, with a specific partitioning and mapping of parallel software tasks, executed on customized VLIW ASIP processing cores. Experimental results, obtained by means of FPGA-based prototyping and post-floorplanning power evaluation on a 40nm technology library, assess the performance and hardware-related costs of the considered configurations. The reported power figures demonstrate the usability of the MPSoC paradigm within the processing of bio-electrical signals and show the benefits achievable by the exploitation of the instruction-level parallelism within tasks
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