1,721,759 research outputs found
Synthesising Energy-Efficient Embedded Systems with LOPOCOS
No full textIn this paper, we introduce the LOPOCOS (Low Power Co-synthesis) system, a prototype CAD tool for system level co-design. LOPOCOS targets the design of energy-efficient embedded systems, implemented as heterogeneous distributed architectures. In particular, it is designed to solve the specific problems involved in architectures that include dynamic voltage scalable (DVS) processors. The aim of this paper is to demonstrate how LOPOCOS can support the system designer in identifying energy-efficient hardware/software implementations for the desired embedded systems. Hence, highlighting the necessary optimisation steps during design space exploration for DVS enable architectures. The optimisation steps carried out in LOPOCOS involve component allocation and task/communication mapping as well as scheduling and dynamic voltage scaling. LOPOCOS has the following key features, which contribute to this energy efficiency. During the voltage scaling valuable power profile information of task execution is taken into account, hence, the accuracy of the energy estimation is improved. A combined optimisation for scheduling and communication mapping based on genetic algorithm, optimises simultaneously execution order and communication mapping towards the utilisation of the DVS processors and timing behaviour. Furthermore, a separation of task and communication mapping allows a more effective implementation of both task and communication mapping optimisation steps. Extensive experiments are conducted to demonstrate the efficiency of LOPOCOS. We report up to 38% higher energy reductions compared to previous co-synthesis techniques for DVS systems. The investigations include a real-life example of an optical flow detection algorithm
Synthesizing Energy-Efficient Embedded Systems with LOPOCOS
No full textIn this paper, we introduce the LOPOCOS (Low Power Co-synthesis) system, a prototype CAD tool for system level co-design. LOPOCOS targets the design of energy-efficient embedded systems, implemented as heterogeneous distributed architectures. In particular, it is designed to solve the specific problems involved in architectures that include dynamic voltage scalable (DVS) processors. The aim of this paper is to demonstrate how LOPOCOS can support the system designer in identifying energy-efficient hardware/software implementations for the desired embedded systems. Hence, highlighting the necessary optimisation steps during design space exploration for DVS enable architectures. The optimisation steps carried out in LOPOCOS involve component allocation and task/communication mapping as well as scheduling and dynamic voltage scaling. LOPOCOS has the following key features, which contribute to this energy efficiency. During the voltage scaling valuable power profile information of task execution is taken into account, hence, the accuracy of the energy estimation is improved. A combined optimisation for scheduling and communication mapping based on genetic algorithm, optimises simultaneously execution order and communication mapping towards the utilisation of the DVS processors and timing behaviour. Furthermore, a separation of task and communication mapping allows a more effective implementation of both task and communication mapping optimisation steps. Extensive experiments are conducted to demonstrate the efficiency of LOPOCOS. We report up to 38% higher energy reductions compared to previous co-synthesis techniques for DVS systems. The investigations include a real-life example of an optical flow detection algorithm
Co-Synthesis of Energy-Efficient Multi-Mode Embedded Systems with Consideration of Mode Execution Probabilities
No full textWe present a novel co-design methodology for the synthesis of energy-efficient embedded systems. In particular, we concentrate on distributed embedded systems that accommodate several different applications within a single device, i.e., multimode embedded systems. Based on the key observation that operational modes are executed with different probabilities, that is, the system spends uneven amounts of time in the different modes, we develop a new co-design technique that exploits this property to significantly reduce energy dissipation. Energy and cost savings are achieved through a suitable synthesis process that yields better hardware-resource-sharing opportunities. We conduct several experiments, including a realistic smart phone example, that demonstrate the effectiveness of our approach. Reductions in power consumption of up to 64% are reported
IEE Proceedings: Computers and Digital Techniques Special issue on "Design and Test Conference in Europe", DATE 03
No full textEditorial Special Issue on DATE03 Design and Test in Europe (DATE) is the main European conference that addresses all topics of research into technologies for electronic and embedded systems engineering. This covers design (hardware and embedded software), verification and test, algorithms and tools for design automation of electronic circuits and systems for wireless communications, multimedia and automotive systems. This Special Issue of IEE Proceedings Computers & Digital Techniques presents extended versions of selected papers from the 6th DATE conference held from 3-7 March 2003 in Munich, Germany. From the 152 papers presented, the executive and technical program committees selected 14 papers that received high grades in the review process for inclusion in this special issue. The authors of 12 papers accepted the invitation and submitted extended versions of their manuscript for peer-reviewing. These papers provide a good cross section of topics covered at DATE 03. The first five papers address “design methods”, including reconfigurable computing, power-aware system and circuit level design, asynchronous design, and networks on chip. The sixth, seventh, eighth, ninth and tenth papers address “CAD tools”, including synthesis of distributed embedded systems, transformation-based formal system design, high level synthesis, and interconnect modelling. The final two papers address “test”, including delay testing and low cost SoC test. The 12 papers are summarised in greater detail below. The first paper, Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling, by Mei et al., describes a modulo scheduling algorithm capable of exploiting loop-level parallelism in coarse-grained reconfigurable architectures, and proposes a graph presentation to model coarse-grained architectures. The algorithm is capable of placing, scheduling and routing operations simultaneously in a modulo-constrained 3D space, and it is evaluated using different tested kernels. The second paper, Scheduling and Mapping of Conditional Task Graph for the Synthesis of Low Power Embedded Systems, by Wu et al., addresses energy minimization in data/control dominated distributed embedded systems using dynamic voltage scaling (DVS). Novel DVS and genetic-based mapping techniques are described, and it is shown that a significant reduction in system energy dissipation is possible when compared with approaches that neglect the availability of DVS. The third paper, Masking the Energy Behaviour of DES Encryption”, by Saputra et al., considers the masking of energy consumption of the Data Encryption Standards algorithm by augmenting the instruction set architecture of a 32-bit processor used in smart cards with secure instruction. To support the secure operations, the necessary modifications to the processor architecture and instruction op-codes are outlined. The effectiveness of the augmented approach is demonstrated by simulation and comparison with existing approaches. The fourth paper, Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design, by Madalinski et al., tackles coding conflicts in Signal Transition Graphs (STGs) used for asynchronous control circuit behavior description. A visualization framework is proposed aimed at facilitating the manual refinement of an STG with complete state coding conflicts (i.e. conflicting cores). Two case studies are included to demonstrate the proposed framework. The fifth paper, Trade Offs in the Design of a Router with Both Guaranteed and Best Effort Services for Networks on Chip, by Rijpkema et al., addresses the problem of managing the design of complex chips by decoupling computation and communication. A router-based NoC architecture that combines guaranteed and best-effort services is proposed and a discussion of the important design issues (trade offs between complexity and efficiency) of such a router is presented. A CMOS prototype of the proposed router is also described. The sixth paper, Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems, by Pop et al., addresses the analysis and optimization of heterogeneous time-triggered and event-triggered systems implemented on multi-cluster embedded networks. Optimization heuristics for system synthesis are proposed, and validated using extensive experimental results including a real-life example. The seventh paper, Development and Application of Design Transformations in ForSyDe, by Sander et al., focuses on the development of a formal system design as an effective methodology for complex systems. The methodology is based on transformational design refinement, the formal basis of the transformations is discussed, and the benefits of transformations are illustrated through the design of an eighth-order FIR filter. The eight paper, Behavioural Specification Allocation to Minimize Bit Level Waste of Functional Units, by Molina et al., addresses the problem of hardware waste in high level synthesis, and proposes an allocation algorithm that minimizes this waste. The algorithm efficiency is demonstrated by extensive experimental results and comparative study with a current approach. The ninth paper, Dynamically Increasing the Scope of Code Motions During High-Level Synthesis of Digital Circuits, by Gupta et al., discusses improving the quality of control-intensive (nested conditionals and loops) high-level synthesis results by proposing dynamic conditional branch balancing technique. Two real-life multimedia and image processing applications are presented to demonstrate the effectiveness of the technique. The tenth paper, Modelling and Evaluation of Substrate Noise Induced by Interconnects, by Martorell et al., investigates the importance of interconnects as a source of substrate noise, and proposes a model for noise coupling between integrated signal interconnects and silicon substrate. The model accuracy is checked against real measured data obtained from 0.35?m test structures. The eleventh paper, Delay Defect Diagnosis Based Upon Statistical Timing Models – The First Step, by Krstic et al., addresses delay testing in deep sub-micron technology, proposes new delay defect diagnosis concepts, and shows how they compare with traditional logic detect diagnosis. Different diagnosis algorithms are described and evaluated using statistical defect injection and delay fault simulation. Finally, in the twelfth paper, Low Cost Software Based Self Testing of RISC Processor Cores, by Kranitis et al., the authors tackle the cost (development and tools) of testing processor cores and present a software-based self-testing methodology that supports low-speed and low-cost external testers. The methodology is validated by designing and testing a RISC processor. The guest editors would like to thank the DATE Executive Committee for supporting the development of this special issue, and would also like to thank April Sparks, Linda Meller and Stuart Govan at the IEE for their assistance in producing this issue. We would also like to sincerely thank all the authors for submitting their papers and the reviewers for keeping up with the very tight schedule that allowed us to complete this special issue as planned in less than seven months. We hope you enjoy this selection of some of the best papers from DATE 03. NORBERT WEHN University of Kaiserslautern, Germany Microelectronic System Design Research Group BASHIR M AL-HASHIMI University of Southampton, UK Electronic System Design Grou
Photovoltaic sample-and-hold circuit enabling MPPT indoors for low-power systems
Full text linkPhotovoltaic (PV) energy harvesting is commonly used to power autonomous devices, and maximum power point tracking (MPPT) is often used to optimize its efficiency. This paper describes an ultra low-power MPPT circuit with a novel sample-and-hold and cold-start arrangement, enabling MPPT across the range of light intensities found indoors, which has not been reported before. The circuit has been validated in practice and found to cold-start and operate from 100 lux (typical of dim indoor lighting) up to 5000 lux with a 55cm2 amorphous silicon PV module. It is more efficient than non-MPPT circuits, which are the state-of-the-art for indoor PV systems. The proposed circuit maximizes the active time of the PV module by carrying out samples only once per minute. The MPPT control arrangement draws a quiescent current draw of only 8µA, and does not require an additional light sensor as has been required by previously-reported low-power MPPT circuits
Design optimization of the phase change material integrated solar receiver: A numerical parametric study
No full textDish-Micro Gas Turbine (D-MGT) systems can be an effective way of power production (<100 kW) in rural areas having limited access to electricity. In such no fuel assisted systems, the stability of the input thermal power to the MGT is an important concern as MGT is sensitive to the temperature variations caused by the natural fluctuation of the solar flux. To reduce this effect, a novel solar receiver has been proposed integrated with a Phase Change Material (PCM) for the short-term thermal energy storage. The proposed receiver is cylindrical shaped filled with PCM, with a conical cavity on the front surface and heat transfer fluid tubes immersed in the PCM. This paper deals with the investigation of the optimum design point of the proposed receiver based on the required input parameters of the MGT. The numerical simulations have been conducted using Computational Fluid Dynamic methods to pre-evaluate the effect of many controlling parameters on the temperature, PCM liquid fraction, pressure loss and outlet thermal power of the receiver. Surface-to-Surface (S2S) radiation model has been employed along with the ray-tracing model for the constant concentrated solar flux of 500 kW/m2 on the receiver aperture surface. The influencing factors considered in this study include the high-temperature PCMs, receiver cavity dimensions, incident solar flux, hot wall thickness, tube diameter and the number of the tubes, pressure drop inside the tubes and the inlet mass flow rate. Results demonstrate the considerable effect of each variable on the receiver output parameters, and this leads to the identification of optimum design point. The result of the study offers valuable guidelines for the receiver development for further experimentation
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
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