1,720,979 research outputs found
Techniques to Save Energy in Heterogeneous Multicore Architectures under QoS Constraints [Elektronisk resurs]
No full textTypically, applications are run with available system resources leading to over-provisioning of resources which can lead to high energy consumption. If the computational demand is specified, in terms of a Quality of Service (QoS) contract, it is possible to devote just enough resources to applications and thereby reduce energy consumption. Modern heterogeneous multicore platforms, such as ARM big.LITTLE, typically provide a multidimensional space of resources, called configuration space, such as Voltage-Frequency (V-F) settings, thread count and processor types, which can be configured at run-time to open up new opportunities for resource management. This thesis presents techniques to improve energy efficiency under the constraint of QoS by managing the resource allocation at run-time for applications run on heterogeneous multicore platforms. The applications considered are iterative with a computational deadline associated with each loop iteration. The proposed techniques apply to a framework that uses applications’ outer loop iterations as a means for progress-tracking and prediction of the execution time. A first contribution of the thesis is a resource management technique for single-threaded applications that uses core type (e.g. big or little cores) and V-F settings as a configuration space to select a configuration, for each iteration, based on the execution-time prediction of future iterations and computational deadlines. The thesis shows that an energy saving of 25% over the race-to-idle state-of-the-art technique is achieved without missing any deadlines. This scheme incurs only 0.6% and 0.8% of timing and energy overheads, respectively. A second contribution of the thesis is a novel resource-management policy for multi-threaded applications. Here, the configuration space is extended to also consider the thread count, i.e., the number of cores assigned to multi-threaded applications. The proposed technique first chooses the most energy-efficient configuration that meets the computational deadline. Since an iteration typically finishes before the deadline, the proposed technique collects the generated execution-time slack over subsequent iterations with the goal of selecting a configuration that can save more energy. To allow for on-line exploration of the configuration space, at low overhead, a third contribution of the thesis is an online, low-overhead prediction method based on interpolation, that measures the execution statistics at end points of each configuration-space dimension and interpolates the values at intermediate configurations. Overall, the proposed technique saves 61% energy compared to the state-of-the-art race-to-idle technique without missing any deadlines. Further, it only incurs 0.6% and 0.7% of timing and energy overheads, respectively
Evaluation of Digital Power Control Algorithms for Automotive LED Headlights using TMS320F28035 Microcontroller
Get PDFDigital power management solutions offer some distinct advantages over their analog counterparts and are increasingly being employed by power electronics designers these days. The post-implementation flexibility of digital solutions is one of the major advantages. Increasing demands on functionalities like communication, remote fault monitoring and configurability have also fueled this transition from analog to digital control. The possibility of implementing non-linear control algorithms is a major advantage of these solutions. Highly integrated analog components, like analog to digital converters and comparators in modern microcontrollers, have enabled designers to decrease on-board component count and complexity. Digital power management solutions have limitations in performance when compared to analog designs, but rapid performance improvements in microcontrollers (MCUs) certainly create a bright future for digital power management. In this project we have investigated a digital power control implementation for switch mode DC-DC converters. The application under consideration is LEDbased automotive headlights. LEDs (light emitting diodes) have gained foothold in many lighting applications due to the decrease in cost per lumen. The automotive industry has previously employed LEDs in a number of lighting application, like back and interior lighting, and now consider a potential use in headlights. Moreover we wanted to prove the capabilities of the TMS320F28035 MCU that is designed for real-time control applications. The combination of two new avenues of digital power management and LED headlights has raised a few challenges that have been solved in this project. First, the characteristic behavior of LEDs is different from conventional incandescent bulbs. LEDs are controlled by maintaining a constant current through them rather than applying a constant voltage. Switch mode power stages intended to control LEDs inherently operate in voltage mode. Considerable modeling and implementation efforts are required to handle both these contrasting behaviors. Secondly, discrete-time models are required for MCU implementation. Existing control theory predominantly employs continuous-time models. These continuous-time models are required to be converted to discrete-time models to make use of existing models for digital implementation. Discrete-time models that are developed from scratch requires considerable effort. Third, existing testsetups used for analog designs can not be directly used for digital designs. Considerable analysis is required for these modifications. The first step in the design flow is modeling; we have to model converters for controlling current through LEDs. Two solutions are proposed: First, existing continuous-time voltage mode models for converters are used and modified to control LEDs. Later some further modifications are made to convert them to discrete time. Second, a new non-linear and discrete-time model is proposed for controlling LED current using inductor current feedback. Later, the developed model is implemented on TMS320F28035. This MCU contains two heterogeneous processor cores. A pre-implementation analysis is carried out to allocate hardware resources and system bandwidth to different software tasks. The control loop is implemented on a so-called control-law accelerator, as it is optimized for this purpose, while useful features like graphical user interface and diagnostics are implemented on C28x CPU. The initial bandwidth allocation to different software tasks is verified by doing measurements and re-allocation. The initial implementation of different software components is also optimized to enhance performance based on this post-implementation system analysis. Lastly, the implemented control algorithms are verified by performing frequency response measurements. Modifications are made to existing test-setups to suit them to needs of digital power control. Open loop and closed loop measurements are performed under different operating conditions. These measurements are compared with results from the model and used to lay down our final analysis. Recursive design approach is used at each design phase. Moreover previous design phases are revisited whenever necessary to optimize the implementation
Techniques to Save Energy in Heterogeneous Multicore Architectures under QoS Constraints
Get PDFTypically, applications are run with available system resources leading to over-provisioning of resources which can lead to high energy consumption. If the computational demand is specified, in terms of a Quality of Service\ua0(QoS) contract, it is possible to devote just enough resources to applications\ua0and thereby reduce energy consumption. Modern heterogeneous multicore\ua0platforms, such as ARM big.LITTLE, typically provide a multidimensional\ua0space of resources, called configuration space, such as Voltage-Frequency (V-F)\ua0settings, thread count and processor types, which can be configured at run-time\ua0to open up new opportunities for resource management.\ua0This thesis presents techniques to improve energy efficiency under the constraint of QoS by managing the resource allocation at run-time for applications\ua0run on heterogeneous multicore platforms. The applications considered are iterative with a computational deadline associated with each loop iteration.\ua0The proposed techniques apply to a framework that uses applications’ outer loop iterations as a means for progress-tracking and prediction of the execution time.A first contribution of the thesis is a resource management technique for single-threaded applications that uses core type (e.g. big or little cores) and\ua0V-F settings as a configuration space to select a configuration, for each iteration,\ua0based on the execution-time prediction of future iterations and computational\ua0deadlines. The thesis shows that an energy saving of 25% over the race-to-idle\ua0state-of-the-art technique is achieved without missing any deadlines. This\ua0scheme incurs only 0.6% and 0.8% of timing and energy overheads, respectively.\ua0A second contribution of the thesis is a novel resource-management policy\ua0for multi-threaded applications. Here, the configuration space is extended to\ua0also consider the thread count, i.e., the number of cores assigned to multi-threaded applications. The proposed technique first chooses the most energy-efficient configuration that meets the computational deadline. Since an iteration\ua0typically finishes before the deadline, the proposed technique collects the\ua0generated execution-time slack over subsequent iterations with the goal of\ua0selecting a configuration that can save more energy. To allow for on-line exploration of the configuration space, at low overhead, a third contribution of\ua0the thesis is an online, low-overhead prediction method based on interpolation,\ua0that measures the execution statistics at end points of each configuration-space\ua0dimension and interpolates the values at intermediate configurations. Overall,\ua0the proposed technique saves 61% energy compared to the state-of-the-artrace-to-idle technique without missing any deadlines. Further, it only incurs\ua00.6% and 0.7% of timing and energy overheads, respectively
Evaluation of Digital Power Control Algorithms for Automotive LED Headlights using TMS320F28035 Microcontroller
No full textDigital power management solutions offer some distinct advantages over their
analog counterparts and are increasingly being employed by power electronics designers
these days. The post-implementation flexibility of digital solutions is one
of the major advantages. Increasing demands on functionalities like communication,
remote fault monitoring and configurability have also fueled this transition
from analog to digital control. The possibility of implementing non-linear control
algorithms is a major advantage of these solutions. Highly integrated analog
components, like analog to digital converters and comparators in modern microcontrollers,
have enabled designers to decrease on-board component count and
complexity. Digital power management solutions have limitations in performance
when compared to analog designs, but rapid performance improvements in microcontrollers
(MCUs) certainly create a bright future for digital power management.<br><br>
In this project we have investigated a digital power control implementation
for switch mode DC-DC converters. The application under consideration is LEDbased
automotive headlights. LEDs (light emitting diodes) have gained foothold
in many lighting applications due to the decrease in cost per lumen. The automotive
industry has previously employed LEDs in a number of lighting application,
like back and interior lighting, and now consider a potential use in headlights.
Moreover we wanted to prove the capabilities of the TMS320F28035 MCU that is
designed for real-time control applications. The combination of two new avenues
of digital power management and LED headlights has raised a few challenges that
have been solved in this project.<br><br>
First, the characteristic behavior of LEDs is different from conventional incandescent
bulbs. LEDs are controlled by maintaining a constant current through
them rather than applying a constant voltage. Switch mode power stages intended
to control LEDs inherently operate in voltage mode. Considerable modeling
and implementation efforts are required to handle both these contrasting behaviors.
Secondly, discrete-time models are required for MCU implementation.
Existing control theory predominantly employs continuous-time models. These
continuous-time models are required to be converted to discrete-time models to
make use of existing models for digital implementation. Discrete-time models
that are developed from scratch requires considerable effort. Third, existing testsetups
used for analog designs can not be directly used for digital designs. Considerable
analysis is required for these modifications.<br><br>
The first step in the design flow is modeling; we have to model converters
for controlling current through LEDs. Two solutions are proposed: First, existing
continuous-time voltage mode models for converters are used and modified
to control LEDs. Later some further modifications are made to convert them to
discrete time. Second, a new non-linear and discrete-time model is proposed for
controlling LED current using inductor current feedback.<br><br>
Later, the developed model is implemented on TMS320F28035. This MCU
contains two heterogeneous processor cores. A pre-implementation analysis is
carried out to allocate hardware resources and system bandwidth to different software
tasks. The control loop is implemented on a so-called control-law accelerator,
as it is optimized for this purpose, while useful features like graphical
user interface and diagnostics are implemented on C28x CPU. The initial bandwidth
allocation to different software tasks is verified by doing measurements
and re-allocation. The initial implementation of different software components is
also optimized to enhance performance based on this post-implementation system
analysis.<br><br>
Lastly, the implemented control algorithms are verified by performing frequency
response measurements. Modifications are made to existing test-setups to
suit them to needs of digital power control. Open loop and closed loop measurements
are performed under different operating conditions. These measurements
are compared with results from the model and used to lay down our final analysis.
Recursive design approach is used at each design phase. Moreover previous
design phases are revisited whenever necessary to optimize the implementation
Techniques to Improve Energy Efficiency on Heterogeneous Multiprocessors under Timing and Quality Constraints
Get PDFTraditionally, applications are executed without the notion of a computational deadline and often use all available system resources, which leads to higher\ua0energy consumption. User specification of Quality of Service (QoS) constraints,\ua0in terms of completion time and solution quality, opens up for allocation of\ua0just enough resources to an application to finish just in time and thereby save\ua0energy. Modern heterogeneous multiprocessor (HMP) platforms provide a\ua0set of configurable resources, including a frequency range of dynamic voltage\ua0frequency scaling (DVFS), one among a set processor types, and one or a\ua0plurality of processors of each type. They can be configured at run-time to\ua0open up new opportunities for resource management.This thesis presents techniques to reduce energy consumption under QoS\ua0constraints by allocating resources at run-time on heterogeneous multiprocessor platforms targeting sequential and parallel iterative and task-parallel\ua0applications. The proposed techniques rely on a progress-tracking framework\ua0that monitors and predicts how much time is left until the application finishes.\ua0Furthermore, the proposed framework enables the prediction of computation\ua0demand and performance requirements for future iterations or tasks.\ua0The first contribution of this thesis is a resource management technique,\ua0called SLOOP, targeting single-threaded applications. SLOOP allocates resources, i.e., processor type and DVFS, for each iteration to meet deadlines\ua0while using the prediction of computational demand and execution time.The second contribution of this thesis is a resource-management scheme, called SaC, for multi-threaded applications executing on HMPs, where resources\ua0also include the number of processors besides DVFS and processor type. SaC\ua0first chooses the most energy-efficient configuration that meets the deadline.\ua0The proposed technique collects execution-time slack over subsequent iterations\ua0to select a configuration that can save energy.The third contribution of this thesis is a resource manager, called Task-RM, for task-parallel applications executing on HMPs under QoS constraints. Task-RM exploits the variance in task execution times and imbalance between\ua0sibling tasks to allocate just enough resources in terms of DVFS and processor type. It uses an innovative off-line analysis to avoid redoing scheduling analysis\ua0at run-time.Finally, the fourth contribution is a scheme, called Approx-RM, that can exploit accuracy-energy trade-offs in approximate iterative applications. Approx-RM allocates an appropriate amount of resources while guaranteeing timing\ua0and solution quality specifications. Approx-RM first predicts the iteration count required to meet the quality target and then allocates enough resources\ua0on an HMP in terms of DVFS, processor type, and processor count to save\ua0energy while meeting a performance target
Techniques to Improve Energy Efficiency on Heterogeneous Multiprocessors under Timing and Quality Constraints [Elektronisk resurs]
No full textTraditionally, applications are executed without the notion of a computational deadline and often use all available system resources, which leads to higher energy consumption. User specification of Quality of Service (QoS) constraints, in terms of completion time and solution quality, opens up for allocation of just enough resources to an application to finish just in time and thereby save energy. Modern heterogeneous multiprocessor (HMP) platforms provide a set of configurable resources, including a frequency range of dynamic voltage frequency scaling (DVFS), one among a set processor types, and one or a plurality of processors of each type. They can be configured at run-time to open up new opportunities for resource management. This thesis presents techniques to reduce energy consumption under QoS constraints by allocating resources at run-time on heterogeneous multiprocessor platforms targeting sequential and parallel iterative and task-parallel applications. The proposed techniques rely on a progress-tracking framework that monitors and predicts how much time is left until the application finishes. Furthermore, the proposed framework enables the prediction of computation demand and performance requirements for future iterations or tasks. The first contribution of this thesis is a resource management technique, called SLOOP, targeting single-threaded applications. SLOOP allocates resources, i.e., processor type and DVFS, for each iteration to meet deadlines while using the prediction of computational demand and execution time. The second contribution of this thesis is a resource-management scheme, called SaC, for multi-threaded applications executing on HMPs, where resources also include the number of processors besides DVFS and processor type. SaC first chooses the most energy-efficient configuration that meets the deadline. The proposed technique collects execution-time slack over subsequent iterations to select a configuration that can save energy. The third contribution of this thesis is a resource manager, called Task-RM, for task-parallel applications executing on HMPs under QoS constraints. Task-RM exploits the variance in task execution times and imbalance between sibling tasks to allocate just enough resources in terms of DVFS and processor type. It uses an innovative off-line analysis to avoid redoing scheduling analysis at run-time. Finally, the fourth contribution is a scheme, called Approx-RM, that can exploit accuracy-energy trade-offs in approximate iterative applications. Approx-RM allocates an appropriate amount of resources while guaranteeing timing and solution quality specifications. Approx-RM first predicts the iteration count required to meet the quality target and then allocates enough resources on an HMP in terms of DVFS, processor type, and processor count to save energy while meeting a performance target
Going Beyond Counting First Authors in Author Co-citation Analysis
Get PDFThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Variations on the Author
Get PDF“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
Appropriate Similarity Measures for Author Cocitation Analysis
Get PDFWe provide a number of new insights into the methodological discussion about author cocitation analysis. We first argue that the use of the Pearson correlation for measuring the similarity between authors’ cocitation profiles is not very satisfactory. We then discuss what kind of similarity measures may be used as an alternative to the Pearson correlation. We consider three similarity measures in particular. One is the well-known cosine. The other two similarity measures have not been used before in the bibliometric literature. Finally, we show by means of an example that our findings have a high practical relevance.information science;Pearson correlation;cosine;similarity measure;author cocitation analysis
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