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De medica materia libri sex , Joanne Ruellio, Suessionensi, interprete, nunc primum ab ipso Ruellio recogniti et suo nitori restituti...
No full text[Sur la matière médicale (latin). 1537]Contient une table des matièresAvec mode texteOuvrages de référenc
Eine Erfurter Teufelsgeschichte von 1537 / Otto Clemen
Get PDFEINE ERFURTER TEUFELSGESCHICHTE VON 1537 / OTTO CLEMEN
Eine Erfurter Teufelsgeschichte von 1537 / Otto Clemen (1)
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Eine Erfurter Teufelsgeschichte von 1537. (3
Political society in Cumberland and Westmorland 1471-1537
No full textThis thesis is intended as an exploration of the administrative and social structures that existed in political society in Cumberland and Westmorland between 1471 and 1537. It has been conceived as a counterpoint to the work of scholars who have undertaken similar research into the networks of authority and political communities in other periods and regions. It will examine the far northwest of England in the context of the upheavals that were occurring in government and society throughout the kingdom at this time and it will highlight degrees of change and continuity apparent in regional administrative and social networks. The thesis will discuss the impact of the region's distance from the capital and its position as a frontier zone with regards to the effectiveness of royal authority and the persistence of feudal administrative and tenurial structures
Mrs. Ella Martin, 1537 8th Ave.
No full textMrs. Ella Martin, 1537 8th Ave., Nov. 25, 1932. Original sleeve reads: Mrs. Ella Martin, 1537 8th Ave., 11-25-1932https://mds.marshall.edu/carl_photograph_collection/1167/thumbnail.jp
Salmon Macrin s'adresse à Saint-Gelais (1537)
No full textDernière mise à jour : 28 septembre 2014 Jean Salmon Macrin, Salmonii Macini Juliodunen. cubicularii Regii, hymnorum libri sex, Ad J,o. Bellaium S.R.E. Cardinalem amplissimum, Robert I Estienne, 1537 (achevé d'imprimer : 7 février 1537). "Ad Mellinum Sangelasium Horticlausi Antistitem" (incipit : "Quid me Sangelasi usque et usque iurgas"), f. iij r° et v°. Voir ici la numérisation de l'ouvrage. Pour citer cet article : SICARD Claire, « Salmon Macrin s'adresse à Saint-Gelais (1537) », Démêle..
Going Beyond Counting First Authors in Author Co-citation Analysis
Get PDFThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Phase Locked Loop Test Methodology
Get PDFPhase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based. Currently the most commonly used PLL architecture for SOC environments and chipset applications is the Charge-Pump (CP) semi-digital type. This architecture is commonly used for clock synthesis applications, such as the supply of a high frequency on-chip clock, which is derived from a low frequency board level clock. In addition, CP-PLL architectures are now frequently used for demanding RF (Radio Frequency) synthesis, and data synchronization applications. On chip system blocks that rely on correct PLL operation may include third party IP cores, ADCs, DACs and user defined logic (UDL). Basically, any on-chip function that requires a stable clock will be reliant on correct PLL operation. As a direct consequence it is essential that the PLL function is reliably verified during both the design and debug phase and through production testing. This chapter focuses on test approaches related to embedded CP-PLLs used for the purpose of clock generation for SOC. However, methods discussed will generally apply to CP-PLLs used for other applications
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