International Journal of Reconfigurable and Embedded Systems (IJRES)
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Wideband frequency-reconfigurable antenna for sub-6 GHz wireless communication
Get PDFThis paper presents a compact dual-band frequency-reconfigurable monopole antenna for sub-6 GHz wireless applications. Using a single PIN diode, the antenna switches between 2.7 GHz and 3.9 GHz bands, achieving bandwidths of 472 MHz and 1130 MHz, respectively, with peak gains up to 1.65 dB. The demand for smaller devices has driven the development of compact antennas capable of operating across multiple bands. The main benefits of this antenna include its compact size, enhanced bandwidth, and design simplicity, which is achieved by integrating slots into the patch and introducing a tiny slot etched over the ground plane. The antenna is created using an FR4 material with a thickness of 1.6 mm and dimensions of 25×15 mm². The antenna prototype was fabricated and tested to validate its performance. Simulation optimization reveals that the antenna operates with a gain of 0.9–1.65 dB and a bandwidth of (472–1130 MHz). The design also achieves a VSWR of less than 1.3 and a radiation efficiency between 74% and 78%. The performance enhancement of the reconfigurable antenna was fine-tuned utilizing microwave solvers in both computer simulation technology (CST) and advance design system (ADS)
Finite element analysis method as an alternative for furniture prototyping process and product testing
Get PDFIn the current furniture industry, making furniture goes through many steps. There are ordering materials, designing, building a prototype, and testing samples. This process is considered quite complex, requiring significant costs, and lengthy production time. The application of finite element analysis (FEA) can be a solution to simulate the furniture manufacturing process. Objective of this research was to determine FEA could substitute making and test prototype furniture thereby saving costs and time. This method utilizes ANSYS 18.1 software for more accurate and rapid calculations, incorporating load variables of 400 N, 600 N, 800 N, and 1,000 N, along with gravitational acceleration of 10 \frac{m}{s^2}. The research evaluates the difference (expressed as a percentage) between the results obtained from simulations and those obtained directly from experiments, considering maximum equivalent stress, maximum principal stress, and total deformation values. The final step involves comparing the simulation with direct testing in terms of cost and time. The research results show an average error factor of 5% across all aspect. In terms of cost, the method can save 1,807 USD and reduce production time by up to one month. From these findings, it can be concluded that the process of prototyping and sample testing can be replaced using the finite element method
Performance analysis of parallel prefix adders developed with field programmable gate array technology
Get PDFIn many digital systems like high-performance computing and digital signal processing, parallel prefix adders are vital. Field programmable gate array (FPGA) technology is a well-known platform for developing parallel prefix adders. FPGA performance depends on bit size of the adder, the adder structure chosen, and the implementation specifications. An examination of the performance and area of parallel prefix adders developed using FPGA technology is presented in this research work. We look into how different design factors, such as the adder structure and the number of input bits, affect the performance and area of parallel prefix adders. The different adders used are Sklansky, Kogge-Stone, Brent-Kung, Han-Carlson, and Ladner-Fisher adders. These adders are implemented using Verilog hardware description language (Verilog HDL) on FPGA boards. The performance is significantly influenced by choice of adder structure and design factors optimized for area or performance. The suggestions for choosing the best adder structure and design factors for the best performance or optimized area are obtained from the synthesis results. Ladner-Fisher adders is best parallel prefix adder with respect area and performance compared with the Sklansky, Kogge-Stone, Brent-Kung and Han-Carlson. Our synthesis can be used as a guide for designers looking to construct specific hardware on FPGA
Enhanced fault detection in photovoltaic systems using an ensemble machine learning approach
Get PDFMalfunctioning of photovoltaic (PV) systems is a main issue affecting solar panels and other related components. Detecting such issues early leads to efficient energy production with low maintenance costs and high system performance consistency. This paper proposed an ensemble model (EM) for fault detection (FD) in PV systems. The proposed model utilized advanced machine learning algorithms containing random forest (RF), k-nearest neighbors (KNN), and gradient boosting (GB). Traditional approaches often do not handle the several situations that PV systems can have. Our EM leveraged the power of GB’s algorithm in handling complex data patterns through iterative boosting, KNN’s capability in capturing local data structures, and RF’s strength in handling overfitting and noise through its tree structure randomness. Combining these models enhanced fault detection capabilities, providing excellent accuracy compared to individual models. To evaluate the performance of our EM, different experiments were conducted. The results demonstrated substantial improvements in detection fault, achieving an accuracy rate of 95%. This accuracy rate considered high underscores the model’s capability to handle fault detection of PV systems, posing a consistent solution for instant fault detection and maintenance scheduling
Exploring the landscape of approximate subtraction methods in ASIC platform
Get PDFApproximate computing has emerged as a crucial technique in modern computing, offering significant benefits for error-resilient applications. Error resilient applications include signal, image, audio processing, and multimedia. These applications will accept the errored results with some degree of tolerance. This approach allows these applications to process and embrace data that may deviate slightly from perfect accuracy. The utility of approximate computing extends to both hardware and software domains. In hardware, arithmetic units are particularly important, among that approximate subtractors have gained attention for their role in these units. A comparative study was conducted on various approximate subtractors from existing literature, considering structural analysis in all scenarios. These approximate subtractors are coded in Verilog hardware description language (HDL) and synthesized in Synopsys electronic design automation (EDA) Tool using Taiwan Semiconductor Manufacturing Company (TSMC) 65 nm technology. Out of the available choices, approximate subtractor 3 is particularly well-suited for processing higher bit data due to its reduced hardware complexity and minimal error. Notably, it outperforms exact subtractors by achieving a notable reduction of 20% in the area delay product (ADP) and 15% in the power delay product (PDP) as process innovation. These improvements highlight the efficiency and effectiveness of approximate subtractor 3, making it a compelling option for various computing applications which accept the inaccurate results
Classifying IoT firmware security threats using image analysis and deep learning
Get PDFAs the internet of things (IoT) grows, its embedded devices face increasing vulnerability to firmware-based attacks. The lack of robust security mechanisms in IoT devices makes them susceptible to malicious firmware updates, potentially compromising entire networks. This study addresses the classification of IoT firmware security threats using deep learning and image-based analysis techniques. A publicly available dataset of 32×32 grayscale images, derived from IoT firmware samples and categorized as benignware, hackware, and malware, was utilized. The grayscale images were converted into three-channel RGB format to ensure compatibility with convolutional neural networks (CNNs). We tested multiple pre-trained CNN architectures, including SqueezeNet, ShuffleNet, MobileNet, Xception, and ResNet50, employing transfer learning to adapt the models for this classification task. Both ResNet50 and ShuffleNet achieved exceptional performance, with 100% accuracy, precision, recall, and F1-score. These results validate the effectiveness of our methodology in leveraging transfer learning for IoT firmware classification while maintaining computational efficiency, making it suitable for deployment in resource-constrained IoT environments.
Development of a blockchain-based electronic voting system utilizing national identification number
Get PDFTraditional voting methods in Nigeria face numerous challenges, including logistic issues, security concerns, and allegations of fraud, which undermine public trust. This work develops a blockchain-based electronic voting system (EVS) that leverages the national identification number (NIN) for biometric verification to address these issues. The research identifies the limitations of current blockchain voting solutions, such as implementation complexity, scalability issues, user adoption resistance, and cybersecurity threats and provide a more secure and user-friendly alternative. The system integrates blockchain technology with biometric verification to create an immutable, transparent, and secure voting process. The methodology involves designing a system architecture that includes a blockchain network, an NIN verification module, and a user interface (UI). Users register using their NIN, authenticate themselves, and cast their votes, which are then encrypted and recorded on the blockchain. The system's functionality was tested using tools like Ganache for local blockchain development, MetaMask for Ethereum wallet integration, and Solidity for writing smart contracts. Results from the implementation indicate significant improvements in security, transparency, and user accessibility compared to traditional voting systems. The user authentication test achieved a 100% valid login success rate and 0% invalid login attempts. Meanwhile, the voting test accuracy was 100%
Hardware design for fast gate bootstrapping in fully homomorphic encryption over the Torus
Get PDFFully homomorphic encryption (FHE) is a promising solution for privacy preserving computations, as it enables operations on encrypted data. Despite its potential, FHE is associated with high computational costs. As the theoretical foundations of FHE mature, mounting interest is focused towards hardware acceleration of established FHE schemes. In this work, we present a hardware implementation of the fast Fourier transform (FFT) tailored for polynomial multiplication and aimed at accelerating gate bootstrapping in Torus fully homomorphic encryption (TFHE) schemes. Our study includes an extensive design-space exploration at various implementation levels, leveraging parallel streaming data to reduce computational latency. We introduce a new algorithm to expedite modular polynomial multiplication using negative wrapped convolution. Our implementation, conducted on reconfigurable hardware, adheres to the default TFHE parameters with 1024-degree polynomials. The results demonstrate a significant performance enhancement, with improvements of up to 30-fold, depending on the FFT design parameters. Our work contributes to the ongoing efforts to optimize FHE, paving the way for more efficient and secure computations
Machine learning methods for energy sector in internet of things
Get PDFThis research paper focuses on exploring machine learning studies and conducting a comparative analysis of their advantages, disadvantages, implementation environments, and algorithms. A key aspect of the study involves evaluating the energy efficiency using machine learning algorithms to predict energy consumption. Additionally, a feature selection algorithm is employed to rank the features, with the highest-ranking feature identified as one of the most significant. The experimentation is conducted using the Weka tool, incorporating several machine learning algorithms such as linear regression, k-nearest neighbors, decision stump, radial basis function (RBF) network, and isotonic regression. The RBF algorithm, which relies on RBF, shares similarities with neural network algorithms. Results indicate a minimum error value of 1.546 for cooling load and 1.364 for heating load. The random forest algorithm emerges as the most suitable choice within the context of this study
Design and development of multiband multi-mode frequency reconfigurable CPW-fed antenna for 5G wireless communication
Get PDFThis research develops, simulates, fabricates and measured a coplanar waveguide (CPW)-fed multiband multi-mode frequency reconfigurable antenna for 5G wireless communication. The antenna is design on Rogers RT5880 substrate with a dielectric constant of 2.2, a thickness of 0.508 mm, and a loss tangent (tanδ) of 0.0009 and the dimension is 30×28×0.508 mm3. The presented antenna has shown good impedance matching with reflection coefficients ranging from -14.82 to -50.36 dB at different frequencies between 6 GHz to 24 GHz. The presented frequency reconfigurable antenna design includes four PIN diodes, resistors, and inductors, enabling 16 different configurations. The simulated outcomes showed varied S parameter values and gains, demonstrating the antenna's flexibility. Measurements were taken using vector network analyzer (VNA) and anechoic chamber to assess reflection coefficient (|S11|) and gain, confirming the antenna's performance. The antenna's ability to reconfigure dynamically without losing signal integrity makes it suitable for 5G wireless applications. It meets and exceeds the requirements for multiband operation, validated by comprehensive simulations and measurements, showing its potential for wide use