International Journal of Reconfigurable and Embedded Systems (IJRES)
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Performing the classification of pulsation cardiac beats automatically by using CNN with various dimensions of kernels
Get PDFThe clinical indication of arrhythmia identifies specific aberrant circumstances in heart pumping that may be detected using electrical impulses during conduction or by allowing a little amount of current to travel through the electrodes, disrupting the cardiac muscle's resistance. The electrocardiogram (ECG) is one of the most important instruments for detecting cardiac arrhythmia since it is the most least intrusive and effective procedure. Physically or visually inspecting the heart is time-consuming and difficult, hence the development of computer aided diagnosis (CAD) is being developed to aid clinical decision-making. In this suggested research, a convolutional neural network (CNN)-based approach is used to automate the heartbeat classification process in order to identify cardiac arrhythmia. The improved enhancement of CNN structure has been implemented in this suggested research. The feature maps are then subjected to the max pooling process. Finally, feature maps are generated by concatenating kernels of different sizes and delivering them as an input to the fully linked layers. The MIT BIH arrhythmia database is used to implement this approach, and the total average accuracy is 99.21%. The proof of the suggested study's efficiency and efficacy in identifying cardiac arrhythmia has also been done via an experimental compariso
Towards more accurate iris recognition system by using hybrid approach for feature extraction along with classifier
Get PDFIris recognition become one of the most accurate and reliable steadfast human biometric recognition system of the decad. This paper presents an accurate framework for iris recognition system using hybrid algorithm in preprocess and feature extraction section. The proposed model for iris recognition with significant feature extraction was divided into three main levels. First level is having pre-processing steps which are necessary for the desired tasks. Our model deploys on three types of datasets such as UBIRIS, CASIA, and MMU and gets optimal results for performing activity. At last, perform matching process with decision based classifier for iris recognition with acceptance or rejection rates. Experimental based results provide for analysis according to the false receipt rate and false refusal amount. In the third level, the error rate will be checked along with some statistical measures for final optimal results. Constructed on the outcome the planned method provided the most efficient effect as compared to the rest of the approach
Design and performance analysis of efficient hybrid mode multi-ported memory modules on FPGA platform
Get PDFThe multi-ported memories (MPMs) are essential and are part of the parallel computing system for high-performance features. The MPMs are commonly used in most processors and advanced system-on-chip (SoC) for faster computation and high-speed processing. In this manuscript, efficient MPMs are designed using the integration of hierarchical bank division with xor (HBDX) and bank division with remap table (BDRT) approaches. The BDRT approach is configured using remap table with a hash write controlling mechanism to avoid write conflicts. The different multiple read ports are designed using BDX, and HBDX approaches are discussed in detail. The results of 2W4R and 3W4R memory modules are analyzed in detail concerning chip area, operating frequency (MHz), block random access memories (BRAMs), and throughput (Gbps) for different memory depths on virtex-7 field programmable gate array (FPGA). The 2W4R utilizes 2.27% slices, operates at 268 MHz frequency by consuming 64 BRAMs for 16K memory depth. Similarly, the 3W4R uses 2.28% slices, operates at 250 MHz frequency by consuming 96 BRAMs for 16K Memory depth. The proposed designs are compared with existing MPM approaches with better chip utilization (Slices), frequency, and BRAMs on the same FPGA device
Alzheimer’s diseases classification using YOLOv2 object detection technique
Get PDFEarly diagnosis and treatment of Alzheimer's disease (AD) is necessary for the patient safety. Computer-aided diagnosis (CAD) is a useful tool for early diagnosis of Alzheimer's disease (AD). We make two contributions to the solution of this problem in this study. To begin with, we are the first to propose an Alzheimer's disease diagnosis solution based on the MATLAB that does not require any magnetic resonance imaging (MRI) pre-processing. Second, we apply recent deep learning object detection architectures like YOLOv2 to the diagnosis of Alzheimer's disease. A new reference data set containing 300 raw data points for Alzheimer's disease detection/normal control and severe stage (MCI/AD/NC) deep learning is presented. Primary screening cases for each category from the Alzheimer's disease neuroimaging initiative (ADNI) dataset. The T1-weighted Dicom MRI slice in the MP-Rage series in 32-bit DICOM image format and 32-bit PNG are included in this dataset. By using MATLAB’s image label tool, the test data were marked with their appropriate class label and bounding box. It was possible to achieve a detection accuracy of 0.98 for YOLOv2 in this trial without the usage of any MRI preprocessing technology
Circular slot antenna for triband application
Get PDFWe recommend a circular monopole antenna (CMPA) with a central feed to operate in three bands. The antenna is circular and has an 8cm diameter. The suggested antennas' resonance frequency ranges are 2.43 GHz, 5.24 GHz, and 9.61 GHz. The planned CMPA is made up of two circle-shaped slots cut into the radiating patch. The whole structure is supplied via a microstrip feed line and analysed using CST Studio's electromagnetic simulator, which is based on finite integral technique (FIT). To check the structure, the return loss, radiation pattern, voltage standing wave ratio (VSWR), and gain are all examined. The structure's ideal dimensions are determined using a parametric study of three factors: feed position, feed breadth, and ground size. The proposed CMPA is capable of operating in several bands and has good matching impedance in all of them
Energy saving on IoT using LoRa: a systematic literature review
Get PDFThe development of devices connected to the internet is very significant, encouraging the creation of the internet of things (IoT). With remote systems, IoT is not enough to use in case of internet instability. By using long range (LoRa), IoT systems can now solve this problem. Millions of data make IoT-LoRa have to spend a lot of energy. This paper helps discover where recent studies offer a broad perspective on energy savings using the systematic literature review (SLR). The paper extracted 252 articles from IEEE, ACM, MDPI, Springer, Hindawi, ScienceDirect, and IAES. 44 articles passed the specified inclusion and exclusion criteria. The article focuses on knowledge about IoT-Lora, energy saving needs, energy saving factors, and the paper demographics. The author synthesizes studies for that purpose on IoT applications using LoRa
Distinct ρ-based model of silicon N-channel double gate MOSFET
Get PDFGrowing endless demand for digital processing technology, to perform high speed computations with low power utilization and minimum propagation delay, the metal-oxide-semiconductor (MOS) technology is implemented in the areas of very large scale integrated (VLSI) circuit technology. But MOS technology is facing the challenges in linear scaling the transistors with different channel modelling for the present day microelectronic regime. Linear scaling of MOSFET is restricted through short-channel-effects (SCEs). Use of silicon N-channel double gate MOSFETs (DG MOSFETs) in present day microelectronic regime features the short channel effect of MOSFET through a reasaonable forward transfer admittance with the characteristics of varying input capacitance values ratio. In this research paper, a distinct ρ-based model is designed to simulate SCEs through the designed silicon N-channel double gate MOSFETs with the varying front and back gate doping level and surface regions to estimate the varying junction capacitances can limit the intrusion detection systems (IDS) usage in VLSI applications. Analytical model for channel length and simulated model for total internal device capacitance through distinct ρ-based model are presented. The proposed distinct ρ-based model is suitable for silicon nanowire transistors and the effectiveness of the proposed model is validated through comparative results
Customization of GPRS, and Wi-Fi device drivers for PXA270 of Linux OS based barcode scanner
Get PDFTo access any device, it is necessary to have an access point. A device driver is an entry point to access a device. This project is aimed to customize the Wi-Fi and general packet radio service (GPRS) device drivers in Linux OS for PXA270 (Intel Xscale ARM processor). Customizing a device driver is a special way of designing software that can be more easily ported from one architecture to another without rewriting it from scratch. The paper is discussing about the customisation of Wi-Fi and GPRS device driver in Linux OS for PXA270 (Intel Xscale ARM processor). To develop a device driver, it is necessary to understand the processor architecture and Linux kernel internals and other design constraints. Since dynamically loaded driver module is attached to the existing kernel, and any error in the driver will crash the entire system. Resource allocation and implementation for a device is one of the main concerns for device driver developers. The device resources are input/output, memory, IRQs and ports. The required toolchain to build the cross-complier for the Intel Xscale ARM processor was built on Linux platform. The customised device drivers of Wi-Fi, and GPRS was customised, and the customised images are made to port for PXA270 processor architecture on EMX-270 board. With all the supporting parameters the kernel images with drivers are build and ported efficiently. Also, a successful verification and testing had been performed for their functionalities
Design and implementation of an automated office environment system using embedded sensors
Get PDFOffice automation is the process using machines with the help of embedded computing perform the office activities and its tools and applications. The office automated using computer-aided processing stored, visual and audio data to simplify, improve, and automate the power saving and time management of the organization. A very important component of office automation concerns the automation of employee centred activities such as authentication, automatic alerting of appointments and automatic powering on/off personal computer. The employee image is captured using Java media framework, attendance records for all employees is gathered and processed automatically, and they can be accessed from the database on a monthly or weekly basis. The various software and hardware components of the system were developed and integrated to form the Exypnos Office System and validated on real life scenarios. Java proved to be a versatile platform for implementing a project of this nature with diverse requirements. Web camera interfacing and image capturing are implemented in the Java environment with the help of Java media framework (JMF). Java short message service (SMS) application programming interface (API) and Bluetooth technology is used for sending schedules through SMS. Radio frequency identification (RFID) systems use many different frequencies, but the most common and widely used and supported by our reader is 125 kHz. Office automation systems have more benefits to an organization. The project is implemented on MS Windows platform and in future can be implemented in Linux platform
An efficient multi-level cache system for geometrically interconnected many-core chip multiprocessor
Get PDFMany-core chip multiprocessor offers high parallel processing power for big data analytics; however, they require efficient multi-level cache and interconnection to achieve high system throughput. Using on-chip first level L1 and second level L2 per core fast private caches is expensive for large number of cores. In this paper, for moderate number of cores from 16 to 64, we present a cost and performance efficient multi-level cache system with per core L1 and last level shared bus cache on each bus line of a cost-efficient geometrically bus-based interconnection. In our approach, we extracted cache hit and miss concurrencies and applied concurrent average memory access time to more accurately determine the cache system performance. We conducted least recently used cache policy-based simulation for cache system with L1, with L1/L2, and with L1/shared bus cache. Our simulation results show that an average system throughput improvement of 2.5x can be achieved by using system with L1/shared bus cache system compared to using only first level L1 or L1/L2. Further, we show that the throughput degradation for the proposed cache system is only within 5% for a single bus fault, suggesting a good bus fault tolerance