International Journal of Reconfigurable and Embedded Systems (IJRES)
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A condition-based distributed approach for secured privacy preservation of nodes in wireless sensor networks IoT
Get PDFThe fast expansion of wireless sensor network-internet of things (WSN-IoT) in recent years has led to the adoption of a vital infrastructure. Adversaries who work together to carry out privacy-related attacks and capture sensitive information from critical infrastructure for a range of personal, political, and commercial purposes, thus security and node preserving have been one of the key areas of research in WSN-IoT. Existing security and privacy research work focuses on cryptography, either which is less efficient, or it majorly focuses on securing the network, which further leads to exposing the nodes to the vulnerability in terms of privacy in the network. This research develops condition-based distributed privacy-preserving (CDPP) approach to preserve the sensor node privacy; the CDPP algorithm develops a condition based on which the nodes' vulnerable information is preserved and not accessed by the compromised nodes. CDPP architecture is evaluated considering the amount of misclassified nodes for safeguarding the node in the network. CDPP is evaluated by inducing the corrupt nodes and further comparing the model with existing low energy adaptive clustering hierarchy (LEACH) based on classification, misclassification and throughput. Furthermore, comparative analysis proves the marginal improvisation in terms of discussed parameter against existing protocol
Approximate single precision floating point adder for low power applications
Get PDFWith an increasing demand for power-hungry data-intensive computing, design methodologies with low power consumption are increasingly gaining prominence in the industry. Most of the systems operate on critical and noncritical data both. An attempt to generate a precision result results in excessive power consumption and results in a slower system. For noncritical data, approximate computing circuits significantly reduce the circuit complexity and hence power consumption. In this paper, a novel approximate single precision floating point adder is proposed with an approximate mantissa adder. The mantissa adder is designed with three 8-bit full adder blocks. In this paper, a detailed mathematical background, and proposed design approach in terms of the circuit configuration and truth tables are discussed. Additionally, a concept of switching between exact computing and approximate computing is analysed considering an approximate carry look-ahead adder. The delay and power consumption for the exact operating mode and approximate operation mode considering varied window sizes is observed. Performance of the approximate computation is compared against exact computation and varied approximate computing approaches
Hybrid fault tolerant cost aware mechanism for scientific workflow in cloud computing
Get PDFCloud computing provides solutions for diverse commercial and academic applications which is the primary goal. Scientific workflows are used in the cloud-computing environment to analyses large-scale scientific applications. For scientific workflows, many data is required, and a single scientific workflow that includes hundreds of stages, depending on the application's time restrictions, task failures, money limits, incorrect task organization, and task management issues can all hinder the implementation of scientific methods. In light of this, a cloud-based scientific workflow management and scheduling system that is fault-tolerant and data-oriented method are proposed. This research designs a novel hybrid cost-aware fault tolerant (HCFT) mechanism for minimizing the cost. Moreover, HCFT integrates optimal clustering and efficient resource utilization through parallel and distributed execution. Novelty of HCFT lies in novel clustering of the similar task for improvisation, CyberShake, laser interferometer gravitational wave observatory (LIGO), Montage, and sRNA identification protocol using high throughput technology (SIPHT) processes are used in the simulations to evaluate the performance of the proposed approach
Robust embedded access control system based on face and encrypted QR with RPi4
Get PDFFacial-based recognition systems are commonly used for building access control, with the accuracy and computing requirements still being improved. On the other hand, QR codes are gaining rising attention as an input interface to many embedded applications. This paper proposes an embedded access control system that customises both previous techniques to be implemented on the CPU of a low-cost Raspberry Pi 4 computer. The achieved system works smoothly with a frame rate of 8.27 FPS, increasing the accessing control's robustness compared to a system based on face recognition only. It also offers the ability to control the access of unknown faces. In tandem with integration, this strengthens security measures, improves user experience, and outperforms conventional access control approaches, creating an attractive offer for many businesses
Cost and performance aware scheduling technique for cloud computing environment
Get PDFRecently, lot of interest have been put forth by researchers to improve workload scheduling in cloud platform. However, execution of scientific workflow on cloud platform is time consuming and expensive. As users are charged based on hour of usage, lot of research work have been emphasized in minimizing processing time for reduction of cost. However, the processing cost can be reduced by minimizing energy consumption especially when resources are heterogeneous in nature; very limited work have been done considering optimizing cost with energy and processing time parameters together in meeting task quality of service (QoS) requirement. This paper presents cost and performance aware workload scheduling (CPA-WS) technique under heterogeneous cloud platform. This paper presents a cost optimization model through minimization of processing time and energy dissipation for execution of task. Experiments are conducted using two widely used workflow such as Inspiral and CyberShake. The outcome shows the CPA-WS significantly reduces energy, time, and cost in comparison with standard workload scheduling model
Internet of things based smart photovoltaic panel monitoring system
Get PDFSolar energy has the potential to meet the entire world's energy requirements. Previous study revealed that photovoltaic (PV) panel monitoring methods are far more difficult and exclusive. This study examines and proposes an automated internet of things (IoT)-based PV panel monitoring system that allows autonomous monitoring of solar panel properties such as voltage, temperature, humidity, and sun irradiation from anywhere over the internet. Excessive human demand can be reduced by collecting data from solar panels. Many data sets can be collected frequently; for example, thousands of data points can be collected each minute. Continuous monitoring is achievable by gathering real-time data. Because there is no possibility of human error, highly accurate data can be generated
Proximate node aware optimal and secure data aggregation in wireless sensor network based IoT environment
Get PDFInternet of things (IoT) has become one of the eminent phenomena in human life along with its collaboration with wireless sensor networks (WSNs), due to enormous growth in the domain; there has been a demand to address the various issues regarding it such as energy consumption, redundancy, and overhead. Data aggregation (DA) is considered as the basic mechanism to minimize the energy efficiency and communication overhead; however, security plays an important role where node security is essential due to the volatile nature of WSN. Thus, we design and develop proximate node aware secure data aggregation (PNA-SDA). In the PNA-SDA mechanism, additional data is used to secure the original data, and further information is shared with the proximate node; moreover, further security is achieved by updating the state each time. Moreover, the node that does not have updated information is considered as the compromised node and discarded. PNA-SDA is evaluated considering the different parameters like average energy consumption, and average deceased node; also, comparative analysis is carried out with the existing model in terms of throughput and correct packet identification
Task level energy and performance assurance workload scheduling model in distributed computing environment
Get PDFScientific workload execution on distributed computing platform such as cloud environment is time intense and expensive. The scientific workload has task dependencies with different service level agreement (SLA) prerequisite at different levels. Existing workload scheduling (WS) design are not efficient in assuring SLA at task level. Alongside, induce higher cost as majority of scheduling mechanisms reduce either time or energy. In reducing, cost both energy and makespan must be optimized together for allocating resource. No prior work has considered optimizing energy and processing time together in meeting task level SLA requirement. This paper present task level energy and performance assurance (TLEPA)-WS algorithm for distributed computing environment. The TLEPA-WS guarantees energy minimization with performance requirement of parallel application under distributed computational environment. Experiment results shows significant reduction in using energy and makespan; thereby reduces cost of workload execution in comparison with various standard workload execution models
FPGA in hardware description language based digital clock alarm system with 24-hr format
Get PDFCurrently, digital clock adapts microprocessor or microcontroller system. Performance of speed and reconfigurability issue become a main concern in digital clocks. New additional feature may be introduced in digital clocks in the future. Field programmable gate array (FPGA) offer better performance of speed and reconfiguration features. Based on these advantages, it is essential to study or explore the digital clock with FPGA design. The objective in this study is to create a hardware description language (HDL)- based digital clock with alarm system and implement it onto the Altera DE2- 115 board. Using Verilog HDL language in Quartus Prime 20.1 Lite Edition software, all submodule components is developed and being test benched using ModelSim-Altera Starter Edition 13.1 to ensure the correct functionality. Then all inputs and outputs will be assigned through pin assignment in the software. For verification purpose, it will be downloaded to the Altera DE2-115 board. In conclusion, the file has been successfully implemented to the board and the digital clock with alarm is fully functional as expected. This was proved by the alarm signal, time adjustment and display of the three-display mode which is clock, alarm, and input where each mode carries their own functions as expected
Channel access mechanism for maximizing throughput with fairness in wireless sensor networks
Get PDFThe spectrum scarcity problem of wireless sensor networks (WSNs) is improved through amalgamation of cognitive radio networks (CRNs) into WSNs. However, spectrum allocation to secondary users (SUs) is challenging in cognitive radio wireless sensor networks (CR-WSNs) as channel is already crowded and at same time should not induce interference to primary users (PUs). In designing efficient spectrum access model for CR-WSNs recent work have adopted machine-learning game theory (GT) and statistical model. However, the major limitation of existing spectrum access model they fail to assure access fairness with maximal throughput with minimal collision. This work presents a maximizing channel access fairness model to handle the research challenges. To boost CR-WSN performance, the throughput maximization using channel access fairness (TMCAF) employs shared and non-shared channel access designs. Experiment outcome shows throughput is improved and collision in network is reduced in comparison with state-of-art channel access models