1,720,991 research outputs found
High quality Schottky contacts for limiting leakage currents in Ge based Schottky barrier MOSFETs
No full textThe vertical metal insulator semiconductor tunnel transistor: A proposed Fowler-Nordheim tunneling device
No full textWe propose a new field-effect transistor, the vertical metal insulator semiconductor tunnel transistor (VMISTT) which operates using gate modulation of the Fowler-Nordheim tunneling current through a metal insulator semiconductor (M-I-S) diode. The VMISTT has significant advantages over the metal-oxide-semiconductor field-effect transistor in device scaling. In order to allow room-temperature operation of the VMISTT, the tunnel oxide has to be optimized for the metal-to-insulator barrier height and the current-voltage characteristics. We have grown TiO2 layers as the tunnel insulator by oxidizing 7 and 10 nm thick Ti metal films vacuum-evaporated on silicon substrates, and characterized the films by current-voltage and capacitance-voltage techniques. The quality of the oxide films showed variations, depending on the oxidation temperatures in the range of 450-550 degrees C. Fowler-Nordheim tunneling was observed at low temperatures at bias voltage of 2 V and above and a barrier height of approximately 0.4 eV was calculated. Leakage currents present were due Schottky-barrier emission at room-temperature, and hopping at liquid nitrogen temperature
Fabrication of low loss coplanar waveguides on gold-doped Czochralski-silicon
No full textCoplanar waveguides fabricated on gold-doped Czochralski-silicon show reduced losses. Gold atoms implanted into silicon substrates compensate for background free carriers introduced by impurities in the material. This leads to an increased silicon resistivity which exhibits lower microwave absorption. High frequency measurements in 1-40 GHz range of coplanar waveguides fabricated on gold-doped silicon show attenuation reductions up to 70%, highlighting the benefits of deep level compensation of shallow level impurities in silicon using gold
Polycrystalline Silicon - Germanium Emitters for Gain Control, With Application to SiGe HBTs
No full textThis paper investigates germanium incorporation into polysilicon emitters for gain control in SiGe heterjunction bipolar transistors. A theory for the base current of a polySiGe emitter is developed, which combines the effects of the polySiGe grains, the grain boundaries and the interfacial layer at the polySiGe/Si interface into an expression for the effective surface recombination velocity of a polySiGe emitter. Silicon bipolar transistors are fabricated with 0,10 and 19 percent Ge clmpared with a control transistor containing no germanium. These values are in good agreement with the theoretical predictions. The competing mechanisms of base current increase by Ge incorporation into the polysilicon and base current decrease due to an interfacial oxide layer are investigated
Depletion isolation effect in Vertical MOSFETS during transition from partial to fully depleted operation
No full textA simulation study is made of floating-body effects (FBEs) in vertical MOSFETs due to depletion isolation as the pillar thickness is reduced from 200 to 10 nm. For pillar thicknesses between 200–60 nm, the output characteristics with and without impact ionization are identical at a low drain bias and then diverge at a high drain bias. The critical drain bias Vdc for which the increased drain–current is observed is found to decrease with a reduction in pillar thickness. This is explained by the onset of FBEs at progressively lower values of the drain bias due to the merging of the drain depletion regions at the bottom of the pillar (depletion isolation). For pillar thicknesses between 60–10 nm, the output characteristics show the opposite behavior, namely, the critical drain bias increases with a reduction in pillar thickness. This is explained by a reduction in the severity of the FBEs due to the drain debiasing effect caused by the elevated body potential. Both depletion isolation and gate–gate coupling contribute to the drain–current for pillar thicknesses between 100–40 nm
Design of 50nm Vertical MOSFET Incorporating a Dielectric Pocket
No full textA new architecture for a vertical MOS transistor is proposed that incorporates a so-called dielectric pocket (DP) for suppression of short channel effects and bulk punch-through. We outline the advantages that the DP brings and propose a basic fabrication process to realize the device. The design issues of a 50-nm channel device are addressed by numerical simulation. The gate delay of an associated CMOS inverter is assessed in the context of the International Technology Roadmap for Semiconductors and the vertical transistor is seen to offer considerable advantages down to the 100-nm node and beyond due to the dual channels and the ability to produce a 50-nm channel length with more relaxed lithography
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
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