353 research outputs found
Neuro-Inspired Computing with Synaptic and Neuronal Devices
No full textPresented on April 9, 2019 at 12:00 p.m. in the Marcus Nanotechnology Building, Room 1116.Shimeng Yu is an associate professor of electrical and computer engineering at Georgia Tech. Prof. Yu’s research interests are nanoelectronic devices and circuits for energy-efficient computing systems. His expertise is on the emerging non-volatile memories (e.g., RRAM, ferroelectrics) for different applications, such as machine/deep learning accelerator, neuromorphic computing, monolithic 3D integration, and hardware security, etc.Runtime: 59:28 minutesNeuro-inspired computing is a new computing paradigm that emulates the neural network for information processing. To enable the large-scale neuromorphic system, it is important to develop compact nanoscale devices to support the synaptic and neuronal functions. In this talk, I will discuss recent progress in this domain that integrates oxide based synaptic and neuronal devices in neuromorphic hardware such as machine/deep learning accelerators. First, I will discuss the desired characteristics of HfO2 based resistive synaptic devices (e.g. analog multilevel states, weight tuning linearity, variation/noises) and NbO2 based oscillation neuron devices, and show the principles of offline training and online training. Next, I will introduce the crossbar array architecture to efficiently implement the weighted sum and weight update operations that are commonly used in the machine/deep learning algorithms, and show array-level experimental demonstrations for these key operations. Lastly, I will show our recent work on doped HfO2 based ferroelectric transistor based synaptic cell design that overcomes the challenges to achieve high training accuracy for online training
SiGe epitaxial memory for neuromorphic computing with reproducible high performance based on engineered dislocations
No full textAlthough several types of architecture combining memory cells and transistors have been used to demonstrate artificial synaptic arrays, they usually present limited scalability and high power consumption. Transistor-free analog switching devices may overcome these limitations, yet the typical switching process they rely on-formation of filaments in an amorphous medium-is not easily controlled and hence hampers the spatial and temporal reproducibility of the performance. Here, we demonstrate analog resistive switching devices that possess desired characteristics for neuromorphic computing networks with minimal performance variations using a single-crystalline SiGe layer epitaxially grown on Si as a switching medium. Such epitaxial random access memories utilize threading dislocations in SiGe to confine metal filaments in a defined, one-dimensional channel. This confinement results in drastically enhanced switching uniformity and long retention/high endurance with a high analog on/off ratio. Simulations using the MNIST handwritten recognition data set prove that epitaxial random access memories can operate with an online learning accuracy of 95.1%.
Capacitive Synaptor With Overturned Charge Injection for Compute-in-Memory
No full textA capacitive synaptic transistor (synaptor) compatible with the fabrication process of conventional Flash memory is proposed for compute-in-memory (CIM) array cells to support energy-efficient inference operations. This synaptor demonstrates the highly reliable endurance characteristic of program/erase (P/E) due to overturned charge injection occurring between a control gate (CG) and a floating gate (FG) rather than between the FG and a channel. On- and off- state capacitances (C-on and C-off) are determined by the area ratio of CG and FG. After optimizing the pulse conditions, we achieved the P/E endurance of at least 10(7) cycles and retention time of 10(4) sec.
Semiconductor Memory Applications in Radiation Environment, Hardware Security and Machine Learning System
No full textabstract: Semiconductor memory is a key component of the computing systems. Beyond the conventional memory and data storage applications, in this dissertation, both mainstream and eNVM memory technologies are explored for radiation environment, hardware security system and machine learning applications.
In the radiation environment, e.g. aerospace, the memory devices face different energetic particles. The strike of these energetic particles can generate electron-hole pairs (directly or indirectly) as they pass through the semiconductor device, resulting in photo-induced current, and may change the memory state. First, the trend of radiation effects of the mainstream memory technologies with technology node scaling is reviewed. Then, single event effects of the oxide based resistive switching random memory (RRAM), one of eNVM technologies, is investigated from the circuit-level to the system level.
Physical Unclonable Function (PUF) has been widely investigated as a promising hardware security primitive, which employs the inherent randomness in a physical system (e.g. the intrinsic semiconductor manufacturing variability). In the dissertation, two RRAM-based PUF implementations are proposed for cryptographic key generation (weak PUF) and device authentication (strong PUF), respectively. The performance of the RRAM PUFs are evaluated with experiment and simulation. The impact of non-ideal circuit effects on the performance of the PUFs is also investigated and optimization strategies are proposed to solve the non-ideal effects. Besides, the security resistance against modeling and machine learning attacks is analyzed as well.
Deep neural networks (DNNs) have shown remarkable improvements in various intelligent applications such as image classification, speech classification and object localization and detection. Increasing efforts have been devoted to develop hardware accelerators. In this dissertation, two types of compute-in-memory (CIM) based hardware accelerator designs with SRAM and eNVM technologies are proposed for two binary neural networks, i.e. hybrid BNN (HBNN) and XNOR-BNN, respectively, which are explored for the hardware resource-limited platforms, e.g. edge devices.. These designs feature with high the throughput, scalability, low latency and high energy efficiency. Finally, we have successfully taped-out and validated the proposed designs with SRAM technology in TSMC 65 nm.
Overall, this dissertation paves the paths for memory technologies’ new applications towards the secure and energy-efficient artificial intelligence system.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201
Scalable in-memory clustered annealer with temporal noise of FinFET for the travelling salesman problem
No full textA Comprehensive Study of Impact of Growth Conditions on Structural and Magnetic Properties of CZT Thin Films
No full textabstract: Soft magnetic materials have been studied extensively in the recent past due to their applications in micro-transformers, micro-inductors, spin dependent memories etc. The unique features of these materials are the high frequency operability and high magnetic anisotropy. High uniaxial anisotropy is one of the most important properties for these materials. There are many methods to achieve high anisotropy energy (Hk) which include sputtering with presence of magnetic field, exchange bias and oblique angle sputtering.
This research project focuses on analyzing different growth techniques of thin films of Cobalt, Zirconium Tantalum Boron (CZTB) and the quality of the films resulted. The measurements include magnetic moment measurements using a Vibrating Sample Magnetometer, electrical measurements using 4 point resistivity methods and structural characterization using Scanning Electron Microscopy. Subtle changes in the growth mechanism result in different properties of these films and they are most suited for certain applications.
The growth methods presented in this research are oblique angled sputtering with localized magnetic field and oblique sputtering without presence of magnetic field. The uniaxial anisotropy can be controlled by changing the angle during sputtering. The resulting film of CZTB is tested for magnetic anisotropy and soft magnetism at room temperature by using Lakeshore 7500 Vibrating Sample Magnetometer. The results are presented, analyzed and explained using characterization techniques. Future work includes magnetic field presence during deposition, magnetic devices of this film with giga hertz range operating frequencies.Dissertation/ThesisMasters Thesis Electrical Engineering 201
Voltage Sense Amplifier (VSA) Design For RRAM Cross-Point Memory Array Structures
No full textabstract: RRAM is an emerging technology that looks to replace FLASH NOR and possibly NAND memory. It is attractive because it uses an adjustable resistance and does not rely on charge; in the sub-10nm feature size circuitry this is critical. However, RRAM cross-point arrays suffer tremendously from leakage currents that prevent proper readings in larger array sizes. In this research an exponential IV selector was added to each cell to minimize this current. Using this technique the largest array-size supportable was determined to be 512x512 cells using the conventional voltage sense amplifier by HSPICE simulations. However, with the increase in array size, the sensing latency also remarkably increases due to more sneak path currents, approaching 873 ns for the 512x512 array
Voltage Controlled Oscillator Based Sigma Delta ADC Design with Noise Coupling Technique
No full textThe rapid advancement of digital technology has driven the demand for high performance Analog to Digital Converters (ADCs) that can seamlessly interface with various analog signals in diverse applications such as communications, medical devices, audio systems, and instrumentation. As systems become increasingly complex, the need for ADCs that provide high resolution, low noise, and efficient power consumption becomes increasingly critical. Traditional ADC architectures often struggle to meet these stringent requirements simultaneously, prompting the exploration of innovative design approaches.
Voltage Controlled Oscillator (VCO) based Sigma Delta (ΣΔ) ADCs have emerged as a promising solution due to their inherent advantages in noise shaping and resolution. The VCO based design leverages the frequency modulation properties of VCOs to convert an analog input signal into a digital output, while the ΣΔ modulation technique ensures effective noise shaping, pushing quantization noise out of the band of interest.[1] This combination provides a pathway to achieve high resolution digital outputs with excellent signal to noise ratios. However, VCO based ΣΔ ADCs face significant challenges related to phase noise, non linearity, and power consumption. Addressing these issues is paramount to fully realizing the potential of VCO based ΣΔ ADCs in high performance applications. One promising approach to mitigate these challenges is the implementation of Noise Coupling techniques.M.S
Current Sensing Amplifier Design for RRAM Crossbar Arrays
No full textabstract: Resistive Random Access Memory (RRAM) is an emerging type of non-volatile memory technology that seeks to replace FLASH memory. The RRAM crossbar array is advantageous in its relatively small cell area and faster read latency in comparison to NAND and NOR FLASH memory; however, the crossbar array faces design challenges of its own in sneak-path currents that prevent proper reading of memory stored in the RRAM cell. The Current Sensing Amplifier is one method of reading RRAM crossbar arrays. HSpice simulations are used to find the associated reading delays of the Current Sensing Amplifier with respect to various sizes of RRAM crossbar arrays, as well as the largest array size compatible for accurate reading. It is found that up to 1024x1024 arrays are achievable with a worst-case read delay of 815ps, and it is further likely 2048x2048 arrays are able to be read using the Current Sensing Amplifier. In comparing the Current Sensing Amplifier latency results with previously obtained latency results from the Voltage Sensing Amplifier, it is shown that the Voltage Sensing Amplifier reads arrays in sizes up to 256x256 faster while the Current Sensing Amplifier reads larger arrays faster
Understanding Correlation Between Memory Window Closure, Leakage and Read Delay Effects for FEFET Reliability Improvement: Role of IL and FE Traps
No full textMemory window (MW) closure, read delay, and gate leakage are three key reliability challenges in ferroelectric (FE) field-effect transistors (FEFETs), all of which have traditionally been analyzed separately. In this work, we exploit dedicated experiments and device simulations to present a detailed study of these three mechanisms in Si-FEFETs with a 10nm layer of FE HZO. The results reveal critical insights into the interplay between trap generation and polarization switching (PS), and the correlation between MW closure, read delay, and leakage current. First, we show that trap generation is accelerated by PS and initially (up to 5e4 cycles) occurs mainly in the interfacial layer (IL). These PS induced traps are slow traps and are found to be responsible for both reduction in MW recovery with read delay and MW closure, demonstrating a strong correlation between the two mechanisms. Finally, we show that leakage current increase is controlled by the generation of HZO traps, which is triggered by internal field redistribution once IL is highly degraded (after MW closure). The engineering of FEFETs to minimize the formation of slow (de)trapping defects in the IL is essential to improve overall reliability of the FEFET device
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