836 research outputs found
DVFS using clock scheduling for Multicore Systems-on-Chip and Networks-on-Chip
Full text linkA modern System-on-Chip (SoC) contains processor cores, application-specific process-
ing elements, memory, peripherals, all connected with a high-bandwidth and low-latency
Network-on-Chip (NoC). The downside of such very high level of integration and con-
nectivity is the high power consumption. In CMOS technology this is made of a dynamic
and a static component. To reduce the dynamic component, Dynamic voltage and Fre-
quency Scaling (DVFS) has been adopted. Although DVFS is very effective chip-wide,
the power optimization of complex SoCs calls for a finer grain application of DVFS.
Ideally all the main components of an SoC should be provided with a DVFS controller.
An SoC with a DVFS controller per component with individual DC-DC converters and
PLL/DLL circuits cannot scale in size to hundreds of components, which are in the
research agenda. We present an alternative that will permit such scaling. It is possible
to achieve results close to an optimum DVFS by hopping between few voltage levels
and by an innovative application of clock-gating that we term as clock scheduling. We
obtain an effective clock frequency by periodically killing some clock cycles of a master
clock. We can apply voltage scaling for some of the periodic clock schedules which yield
effective clock 1/2, 1/3, . . . By dithering between few voltages we obtain results close to
an ideal DVFS system in simple pipelined circuits and in a complex example, a NoC’s
switch.
Again in the context of a NoC, we show how clock scheduling and voltage scaling can
be automatically determined by means of a proportional-integral loop controller that
keeps track of the network load. We describe in detail its implementation and all the
circuit-level issues that we found. For a single switch, result shows an advantage of up
to 2X over simple frequency scaling without voltage scaling.
By providing each NoC’s switch with our simple DVFS controller, power saving at
network level can be significantly more than what a a global DVFS controller can get.
In a realistic scenario represented by network traces generated by video applications
(MPEG, PIP, MWD, VoPD), we obtain an average power saving of 33%.
To reduce static power, the Power-Gating (PG) technique is used and consists in switching-
off power supply of unused blocks via pMOS headers or nMOS footers in series with such
blocks. Even though research has been done in this field, the application of PG to NoCs
has not been fully investigated. We show that it is possible to apply PG to the input
buffers of a NoC switch. Their leakage power contributes about 40-50% of total NoC
power, hence reducing such contribution is worthwhile. We partitioned buffers in banks
and apply PG only to inactive banks. With our technique, it is possible to save about
40% in leakage power, without impact on performance
RECTIFIED DIFFERENTIAL CRYPTANALYSIS OF 16 ROUND PRESENT
No full textRECTIFIED DIFFERENTIAL CRYPTANALYSIS OF 16 ROUND PRESENT
Manoj Kumar , Pratibha Yadav and Meena Kumari
SAG, DRDO, Metcalfe House, Delhi-110054, India
ABSTRACT
In this paper, we have suggested rectifications in differential cryptanalysis of ultra-lightweight block cipher PRESENT reduced to 16 rounds. We have shown that proposed differential attack by Wang [3] on 16 round PRESENT can recover at the most 30 subkey bits, although the author has claimed to recover 32 bits of subkey for last two rounds. We have also computed data complexity and success probability for recovering 30 subkey bits accordingly by the differential attack on 16 round PRESENT.
KEYWORDS
Lightweight block cipher, differential cryptanalysis, PRESEN
DVFS Based on Voltage Dithering and Clock Scheduling for GALS Systems
No full textTo effectively manage power in Globally-Asynchronous Locally-Synchronous (GALS) systems with many interconnected nodes, each should be ideally provided with an individual Dynamic Voltage and Frequency Scaling (DVFS) mechanism. However, full-blown DVFS requires complex voltage regulators and PLL or DLL circuits. To reduce the difficulty of integrating many complex DVFS controllers, we propose a DVFS system that makes use of 1) voltage dithering between a few voltage levels, 2) a scheduler that selectively kills ticks of a high-frequency clock to create an "effective" clock frequency and 3) a local distributed clock-gating mechanism that periodically stalls the registers of a pipeline without incurring the penalties of global clock gating. We report results obtained on a CMOS 45 nm technology and show that the behavior is close to that of an ideal DVFS, even with only two voltage level
A Simple DVFS Controller for a NoC Switch
No full textNetwork-on-Chip (NoC) is the high-performance and scalable alternative to the old-fashioned bus, but yet a costly one as far as power consumption is concerned. Dynamic Voltage and Frequency Scaling (DVFS) is a very effective technique for reducing power consumption. In its typical, bulky incarnation with voltage regulators and PLLs or DLLs for frequency synthesis, though, it does not fit very well the need for individual regulation at the level of NoC's single switch. We propose a simple DVFS mechanism for a NoC switch. It uses just two voltages, high and low, for voltage scaling. For effective frequency scaling a periodic scheduler equipped with a simple counter and a clock-gating logic is used. A feedback control loop chooses the appropriate frequency and voltage pair based on the status of switch's input FIFOs. We report results of simulation and synthesis on a 45nm CMOS technolog
LAURA-NoC: Local Automatic Rate Adjustment in Network-on-Chips With a Simple DVFS
No full textIn this brief, we propose local automatic rate adjustment in network-on-chips (NoC) (LAURA-NoC), a NoC with a distributed approach to dynamic voltage and frequency scaling (DVFS). The utilization of the switch buffers is used in a local feedback loop to automatically determine the appropriate clock frequency and voltage that allow the switch to sustain the rate at its input ports, without a global controller. The DVFS controller is simple and uses 2 voltage and 16 frequency values. We report a significant power saving compared to a global DVFS approach in a 45-nm CMOS technology, 33% on average over four realistic video applications
Power-Gating Technique for Network-on-Chip Buffers
Full text linkA new approach to reducing leakage power in network-on-chip buffers is presented. The non-uniformity of buffer utilisation is leveraged across the network and power-gating is applied to scarcely utilised buffers. Instead of turning-off the buffers completely, a buffer portion is kept turned-on. This design choice has a significant performance benefit because the buffer is always able to receive network packets. Design aspects and trade-offs in a 45 nm CMOS technology are discussed and results obtained over video application benchmarks are presented. It is shown that it is possible to reduce buffer leakage by 40% without performance penalt
Reduction of Leakage Power in Networks-on-Chip with Buffers Power-Gating
No full textA NoC consists of a topology of interconnected switches, usually a regular one like a mesh. Processing elements and memories are connected to the switches. High-performance NoCs consume a relevant fraction of chip power and a large part of this power is consumed by network buffers. We report on our recent work on leakage power reduction of the SRAM buffers that make up the FIFO queues of a NoC switch. In particular we focus on reducing power of SRAM buffers that are not fully utilized. NoC traffic may present large spatial and temporal variations, and so not fully loaded NoC nodes can be reconfigured to save power. We assume that the SRAM buffers can be partitioned in banks and that each bank can be individually put in a low-power state by cutting its power supply via power MOSFETs, a technique termed power-gating
A prospective, multicenter, clinical study to evaluate the safety, pharmacokinetics, and efficacy of bleed outcomes, with HemoRel-A® in severe hemophilia A patients
No full textPurpose: To evaluate efficacy for an on-demand treatment of acute bleeding events, pharmacokinetics, safety, and tolerability of HemoRel-A® in severe hemophilia A. Methods: A total of 44 male subjects with severe hemophilia A with an annualized bleed rate of 12 while on-demand treatment with factor VIII (FVIII) were enrolled in the study and received HemoRel-A® for bleed treatment. The efficacy of HemoRel-A® was evaluated based on a four-point scale (excellent, good, moderate, or none). Six-point pharmacokinetic (PK) assessment was performed following a single dose of 50 IU/kg in 12 subjects after a 7-day wash-out period. Safety evaluations were performed at each visit and inhibitor testing was performed in all patients at screening and end of study. Results: Forty-four male subjects received at least a single dose of the study medication and were included in the intent-to-treat (ITT) analysis and safety outcome. In 23 (7.52%) out of the 306 bleeding events, HemoRel-A® efficacy was rated as excellent, in 272 (88.89 %) bleeds it was rated as good, and in 11 (3.68%) bleeding events it was rated as moderate. No failure of efficacy was noted in any of the bleeding events. Thus overall out of 306 bleeding events, 295 (96.41%) showed excellent or good efficacy. Pharmacokinetic assessment based on plasma FVIII activity measured by the chromogenic assay in 12 patients showed comparative results similar to FVIII preparations. A total of 12 adverse events (AEs) were reported in this study. There was no inhibitor development in this previously treated patients (PTP) cohort. Conclusion: HemoRel-A® was established to be efficacious and safe in the treatment of acute bleeding events in subjects with severe hemophilia A.</p
Binding Characteristics of Anticancer Drug Doxorubicin with Two-Dimensional Graphene and Graphene Oxide : Insights from Density Functional Theory Calculations and Fluorescence Spectroscopy
No full textThere has been a perpetual interest in identifying suitable nano-carriers for drug delivery. In this regard, graphene-based two-dimensional materials have been proposed and demonstrated as drug carriers. In this paper, we have investigated the adsorption characteristics of a widely used anticancer drug, doxorubicin (DOX), on graphene (G) and graphene oxide (GO) by density functional theory calculations and fluorescence and X-ray photoelectron spectroscopies. From the calculated structural and electronic properties, we have concluded that G is a better binder of DOX compared to GO, which is also supported by our fluorescence measurements. The binding of DOX to G is mainly based on strong pi-pi stacking interactions. Consistent with this result, we also found that the sp(2) regions of GO interact with DOX stronger than the sp(3) regions attached with the functional groups; the binding is characterized by pi-pi and hydrogen-bonding interactions, respectively.</p
Collected Papers (Papers of Mathematics or Applied Mathematics), Volume V
No full textThis volum includes 37 papers of mathematics or applied mathematics written by the author alone or in collaboration with the following co-authors: Cătălin Barbu, Mihály Bencze, Octavian Cira, Marian Niţu, Ion Pătraşcu, Mircea E. Şelariu, Rajan Alex, Xingsen Li, Tudor Păroiu, Luige Vlădăreanu, Victor Vlădăreanu, Ştefan Vlăduţescu, Yingjie Tian, Mohd Anasri, Lucian Căpitanu, Valeri Kroumov, Kimihiro Okuyama, Gabriela Tonţ, A. A. Adewara, Manoj K. Chaudhary, Mukesh Kumar, Sachin Malik, Alka Mittal, Neetish Sharma, Rakesh K. Shukla, Ashish K. Singh, Jayant Singh, Rajesh Singh, V.V. Singh, Hansraj Yadav, Amit Bhaghel, Dipti Chauhan, V. Christianto, Priti Singh, and Dmitri Rabounski
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