879 research outputs found
ISA Support for Hardware Resource Partitioning in RISC-V
No full textIn modern computing environments, applications concurrently executing on the same system often compete for shared hardware resources, such as caches and buffers. The ensuing contention can lead to timing interferences, posing significant threats such as deadline misses in real-time systems and the creation of timing channels in secure systems. This work proposes an ISA extension based on the RISC-V Capacity and Bandwith Controller QoS Register Interface (CBQRI). Our proposal enables dynamic, comprehensive temporal and spatial partitioning of shared hardware resources, ensuring the isolated execution times of concurrent applications
Sinirinnan kielellä : Nils-Aslak Valkeapään runouden suhde puhuttuun saamen kieleen
No full textAbstractThis paper illustrates and analyses the connections between spoken Saami and the lyric oeuvre of Nils-Aslak Valkeapää on several levels. Among other things, it provides examples of distinctive morpho-phonological, lexical and syntactic features as well as the use of punctuation marks, fonts, and other layout elements. Of the connections exemplified, the use of dialect in particular is regarded as a manifestation of the local identity of the poet, but the use of certain other features has clearly been motivated by stylistic and aesthetic considerations. As a contextualizing introduction, the author describes the difficulties of a minority writer who was never taught his native Saami language at school and whose first books were published amid the turmoil of constantly changing Saami orthographies. In addition, the role of dialects in Saami literature is discussed on a more general level.Abstract
This paper illustrates and analyses the connections between spoken Saami and the lyric oeuvre of Nils-Aslak Valkeapää on several levels. Among other things, it provides examples of distinctive morpho-phonological, lexical and syntactic features as well as the use of punctuation marks, fonts, and other layout elements. Of the connections exemplified, the use of dialect in particular is regarded as a manifestation of the local identity of the poet, but the use of certain other features has clearly been motivated by stylistic and aesthetic considerations. As a contextualizing introduction, the author describes the difficulties of a minority writer who was never taught his native Saami language at school and whose first books were published amid the turmoil of constantly changing Saami orthographies. In addition, the role of dialects in Saami literature is discussed on a more general level
Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core
No full textMicroarchitectural timing channels use variations in the timing of events, resulting from competition for limited hardware resources, to leak information in violation of the operating system's security policy. Such channels also exist on a simple in-order RISC-V core, as we demonstrate on the open-source RV64GC Ariane core. Time protection, recently proposed and implemented in the seL4 microkernel, aims to prevent timing channels, but depends on a controlled reset of microarchitectural state. Using Ariane, we show that software techniques for performing such a reset are insufficient and highly inefficient. We demonstrate that adding a single flush instruction is sufficient to close all five evaluated channels at negligible hardware costs, while requiring only minor modifications to the software stack
The Philosophy of Social Market Economy: Michel Foucault's Analysis of Ordoliberalism
Full text linkMichel Foucault’s lectures at the Collège de France in 1978–1979 centered on the analysis of power with regard to liberalism. Foucault especially focused on German ordoliberalism and its specific governmentality. Although Foucault’s review of the ordoliberal texts, programs, and books is very faithful, there are some occasional “schematic” simplifications. Our paper will evaluate Foucault’s constitution of an ordoliberal “archive”, though more emphasis will be put on the general importance of the phenomenological orientation in Walter Eucken’s work. Hence, three tasks will guide our paper: first, an analysis of Foucault’s position; second, the phenomenological foundation of the ordoliberal discourse compared to the 18th century liberal discourse, i.e. the way in which Walter Eucken received Husserl. Third, our paper shall raise the subject of the mutual historical-epistemological complementation of philosophy and economics by taking Foucault’s analysis as the starting point. Furthermore, the consequences of a phenomenological, “eidetic” order of the economy will be discussed, focusing mainly on the expansion of competition in social domains. --Foucault,Husserl,Eucken,ordoliberalism,eidetic order of the market,social market economy
AutoCC: Automatic Discovery of Covert Channels in Time-Shared Hardware
Full text linkCovert channels enable information leakage between security domains that should be isolated by observing execution differences in shared hardware. These channels can appear in any stateful shared resource, including caches, predictors, and accelerators. Previous works have identified many vulnerable components, demonstrating and defending against attacks via reverse engineering. However, this approach requires much human effort and reasoning. With the Cambrian explosion of specialized hardware, it is becoming increasingly difficult to identify all vulnerabilities manually.To tackle this challenge, we propose AutoCC, a methodology that leverages formal property verification (FPV) to automatically discover covert channels in hardware that is shared between processes. AutoCC operates at the register-transfer level (RTL) to exhaustively examine any machine state left by a process after a context switch that creates an execution difference. Upon finding such a difference, AutoCC provides a precise execution trace showing how the information was encoded into the machine state and recovered.Leveraging AutoCC’s flow to generate FPV testbenches that apply our methodology, we evaluated it on four open-source hardware projects, including two RISC-V cores and two accelerators. Without hand-written code or directed tests, AutoCC uncovered known covert channels (within minutes instead of many hours of test-driven emulations) and unknown ones. Although AutoCC is primarily intended to find covert channels, our evaluation has also found RTL bugs, demonstrating that AutoCC is an effective tool to test both the security and reliability of hardware designs.CCS CONCEPTS• Security and privacy → Side-channel analysis and countermeasures; Tamper-proof and tamper-resistant designs; Information flow control; • Hardware → Best practices for EDA
On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster
Full text linkWith the shrinking of technology nodes and the use of parallel processor clusters in hostile and critical environments, such as space, run-time faults caused by radiation are a serious cross-cutting concern, also impacting architectural design. This paper introduces an architectural approach to run-time configurable soft-error tolerance at the core level, augmenting a six-core open-source RISC-V cluster with a novel On-Demand Redundancy Grouping (ODRG) scheme. ODRG allows the cluster to operate either as two fault-tolerant cores, or six individual cores for high-performance, with limited overhead to switch between these modes during run-time. The ODRG unit adds less than 11% of a core's area for a three-core group, or a total of 1% of the cluster area, and shows negligible timing increase, which compares favorably to a commercial state-of-the-art implementation, and is 2.5× faster in fault recovery re-synchronization. Furthermore, when redundancy is not necessary, the ODRG approach allows the redundant cores to be used for independent computation, allowing up to 2.96× increase in performance for selected applications
The adaptive market hypothesis and time varying stock market return predictability in the DACH-countries
No full textauthor: Nils KaufmannMasterarbeit University of Innsbruck 201
The adaptive market hypothesis and time varying stock market return predictability in the DACH-countries
No full textauthor: Nils KaufmannMasterarbeit University of Innsbruck 201
The adaptive market hypothesis and time varying stock market return predictability in the DACH-countries
No full textauthor: Nils KaufmannMasterarbeit University of Innsbruck 201
Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning
No full textMicroarchitectural timing channels enable unwanted information flow across security boundaries, violating fundamental security assumptions. They leverage timing variations of several state-holding microarchitectural components and have been demonstrated across instruction set architectures and hardware implementations. Analogously to memory protection, (Ge et al. 2019) have proposed time protection for preventing information leakage via timing channels. They also showed that time protection calls for hardware support. This work leverages the open and extensible RISC-V instruction set architecture (ISA) to introduce the temporal fence instruction fence.t , which provides the required mechanisms by clearing vulnerable microarchitectural state and guaranteeing a history-independent context-switch latency. We propose and discuss three different implementations of fence.t and implement them on an experimental version of the seL4 microkernel (Klein et al. 2014) and CVA6, an open-source, in-order, application class, 64-bit RISC-V core (Zaruba and Benini 2019). We find that a complete, systematic, ISA-supported erasure of all non-architectural core components is the most effective implementation while featuring a low implementation effort, a minimal performance overhead of less than 1%, and negligible hardware costs
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